公开(公告)号：US20090067270A1

公开(公告)日：2009-03-12

申请号：US12116324

申请日：2008-05-07

申请人： Larry Wissel

发明人： Larry Wissel

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/846 ,  G11C29/848

摘要： A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.

摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构包括用于实现存储器列冗余方案的系统。 该系统包括具有多个列的核心阵列和冗余列，每个冗余列被配置用于读取或写入用于转向磁芯阵列中的有缺陷的列的信息和电路的位，其中电路包括一个列多路复用器，其导致具有 存储器列冗余方案包括一个复用级。

公开(公告)号：US20080201675A1

公开(公告)日：2008-08-21

申请号：US12111609

申请日：2008-04-29

申请人： Larry Wissel

发明人： Larry Wissel

IPC分类号： G06F17/50

CPC分类号： G11C29/003 ,  G01R31/31725 ,  G11C11/41 ,  G11C29/50

摘要： A design structure for an integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop. The second delayed version of the clock signal drives the third flip-flop to monitor the second flip-flop delay, the possible “pass set-up” state, and “pass hold” state outputs are determined for the second flip-flop based on a final test state of the second and third flip-flops.

摘要翻译： 集成电路（IC）的设计结构包括用于精确地测量IC设计中包括的触发器的设置和保持时间中的至少一个的电路。 电路使用在IC中的触发器位置确定的数据，并且包括由第一时钟驱动并被配置为将第一时钟的零延迟值提供给第一触发器的第一延迟元件。 电路还包括具有可选延迟的第二延迟元件，第二延迟元件被配置为将第一时钟的第一延迟版本提供给第二触发器，其中第一触发器的输出耦合到 第二个触发器。 第三延迟元件具有可选择的延迟并且与第二延迟元件串联耦合以将第一时钟的第二延迟版本提供给第三触发器，并且第二触发器的输出耦合到 第三个触发器。 时钟信号的第二延迟版本驱动第三触发器以监视第二触发器延迟，可能的“通过建立”状态，并且基于第二触发器确定“通过保持”状态输出 第二和第三个触发器的最终测试状态。

公开(公告)号：US20080071489A1

公开(公告)日：2008-03-20

申请号：US11532252

申请日：2006-09-15

申请人： Larry Wissel

发明人： Larry Wissel

IPC分类号： G06F19/00 ,  G01R29/02

CPC分类号： G11C29/003 ,  G01R31/3016 ,  G01R31/31725 ,  G11C29/50 ,  G11C29/50012

摘要： An integrated circuit (IC) includes circuitry for measuring accurately at least one of set-up and hold times of a flip-flop included in the IC design. The circuitry uses data determined at the location of the flip-flop in the IC, and includes a first delay element driven by a first clock and configured to supply a zero-delay value of the first clock to a first flip-flop. The circuitry also includes a second delay element having a selectable delay, the second delay element configured to supply a first delayed version of the first clock to a second flip-flop, wherein an output of the first flip-flop is coupled to an input of the second flip-flop. A third delay element has a selectable delay and is coupled in series with the second delay element to supply a second delayed version of the first clock to a third flip-flop, and an output of the second flip-flop is coupled to an input of the third flip-flop. The second delayed version of the clock signal drives the third flip-flop to monitor the second flip-flop delay, the possible “pass set-up” state, and “pass hold” state outputs are determined for the second flip-flop based on a final test state of the second and third flip-flops.

摘要翻译： 集成电路（IC）包括用于精确地测量IC设计中包括的触发器的建立和保持时间中的至少一个的电路。 电路使用在IC中的触发器位置确定的数据，并且包括由第一时钟驱动并被配置为将第一时钟的零延迟值提供给第一触发器的第一延迟元件。 电路还包括具有可选延迟的第二延迟元件，第二延迟元件被配置为将第一时钟的第一延迟版本提供给第二触发器，其中第一触发器的输出耦合到 第二个触发器。 第三延迟元件具有可选择的延迟并且与第二延迟元件串联耦合以将第一时钟的第二延迟版本提供给第三触发器，并且第二触发器的输出耦合到 第三个触发器。 时钟信号的第二延迟版本驱动第三触发器以监视第二触发器延迟，可能的“通过建立”状态，并且基于第二触发器确定“通过保持”状态输出 第二和第三个触发器的最终测试状态。

公开(公告)号：US07098721B2

公开(公告)日：2006-08-29

申请号：US10711205

申请日：2004-09-01

申请人： Michael R. Ouellette ,  Larry Wissel

发明人： Michael R. Ouellette ,  Larry Wissel

IPC分类号： H01H37/76

CPC分类号： G11C29/027 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.

摘要翻译： 公开了一种用于低电压编程的集成电路的电子熔丝结构，并结合了差分感测方案。 在Vdd执行感测操作时，以大约1.5倍的Vdd执行编程步骤，这限制了由感测操作引起的电子熔断器的电阻变化。 在感测操作期间，门控晶体管模拟保险丝选择晶体管上的电压降，用于完整的熔丝的情况。 还公开了用于表征电子熔断器的电阻的电路和方法。

公开(公告)号：US20060059393A1

公开(公告)日：2006-03-16

申请号：US11270411

申请日：2005-11-08

申请人： Jeffrey Oppold ,  Michael Ouellette ,  Larry Wissel

发明人： Jeffrey Oppold ,  Michael Ouellette ,  Larry Wissel

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G11C5/005 ,  G11C11/4125 ,  G11C29/787

摘要： A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

摘要翻译： 与RAM相关联的冗余寄存器架构提供了软错误容限。 启用寄存器为包含冗余行和列的替换信息的寄存器提供软错误率保护。 门寄存器确定行或列替换寄存器是否包含特定地址，并且根据需要激活替换寄存器的奇偶校验保护。 更改寄存器架构，使寄存器状态成为大多数寄存器的“无关”状态。 识别对冗余系统至关重要的少量寄存器，并使其变得更加鲁棒。 实现字线和列行替代。 当奇偶校验被激活时，实现纹波奇偶校验方案。

公开(公告)号：US06624677B1

公开(公告)日：2003-09-23

申请号：US10064378

申请日：2002-07-08

申请人： Larry Wissel

发明人： Larry Wissel

IPC分类号： H03K3289

CPC分类号： H03K3/0372 ,  H03K3/0375

摘要： A flip-flop circuit comprising: a master latch circuit; a slave latch circuit coupled to the master latch circuit; and a correction circuit for increasing an amount of charge that can be absorbed by the master latch circuit in response to a soft-error event when the slave latch circuit is in a transparent phase and when both the master and slave latch circuits are storing the same data.

摘要翻译： 一种触发器电路，包括：主锁存电路; 耦合到主锁存电路的从锁存电路; 以及校正电路，用于当从锁存电路处于透明阶段时，当主锁存电路和从锁存电路都存储相同时，响应于软错误事件增加可由主锁存电路吸收的电荷量的校正电路 数据。

公开(公告)号：US5118972A

公开(公告)日：1992-06-02

申请号：US714481

申请日：1991-06-13

申请人： Larry Wissel ,  Terrance J. Zittritsch

发明人： Larry Wissel ,  Terrance J. Zittritsch

IPC分类号： H03K17/567 ,  H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： BiCMOS gate pull-down circuits are disclosed for enhanced downside switching of load capacitance. Two PFETs are connected in series as input to the base of an npn type bipolar transistor. The collector and emitter of the bipolar transistor are connected to the circuit output and ground, respectively. One of the series connected PFETs is gated by a predetermined input signal and the second PFET is controlled by the output of an inverter tied to the collector of the bipolar transistor. Upon saturation of the bipolar transistor, the inverter disrupts flow of charge into the base of the transistor and an NFET tied between the base and ground begins to pull charge from the base. A second NFET may be connected to dissipate charge from the collector either through the base or directly to ground. Various circuit modifications are also discussed.

摘要翻译： 公开了用于增强负载电容下降开关的BiCMOS门下拉电路。 两个PFET串联连接到npn型双极晶体管的基极。 双极晶体管的集电极和发射极分别连接到电路输出和地。 串联连接的PFET之一由预定的输入信号选通，第二PFET由连接到双极晶体管的集电极的反相器的输出控制。 在双极晶体管饱和时，反相器破坏电荷流入晶体管的基极，并且连接在基极和地之间的NFET开始从基极拉电荷。 可以连接第二NFET以从收集器通过基底或直接地到地消散电荷。 还讨论了各种电路修改。