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公开(公告)号：US20030179631A1
公开(公告)日：2003-09-25
申请号：US10395656
申请日：2003-03-21
IPC分类号： H03K019/177
CPC分类号： H03K17/693
摘要： A column redundancy architecture for arrayed parallel processor devices is disclosed. In particular, daisy chained communication between processing elements is preserved after defective memory columns and their associated processing elements are disabled, by setting a bypass circuit within the processing element to be disabled. An address remapping circuit ensures that spare memory columns and associated processing elements replacing the defective memory columns and processing elements can be addressed in a linear column order. The column redundancy architecture is flexible as it permits replacement of arbitrary numbers of series adjacent processing elements as well as non adjacent processing elements with a minimal impact on device performance.
摘要翻译： 公开了用于阵列并行处理器设备的列冗余架构。 特别地，通过将处理元件内的旁路电路设置为禁用，特别地，在缺陷存储器列及其相关联的处理元件被禁用之后，处理元件之间的菊花链式通信被保留。 地址重映射电路确保可以以线性列顺序来寻址替代有缺陷的存储器列和处理元件的备用存储器列和相关联的处理元件。 列冗余架构是灵活的，因为它允许替换任意数量的相邻处理元件以及不相邻的处理元件，对设备性能的影响最小。
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公开(公告)号：US20020067296A1
公开(公告)日：2002-06-06
申请号：US10022932
申请日：2001-12-18
发明人： David A. Brown
IPC分类号： H03M007/00
CPC分类号： H04L12/4641 , H04L45/745 , H04L49/201 , H04L49/351 , H04L49/354
摘要： A method and apparatus is provided for translating an L-bit input signal to a W-bit output signal such as a virtual network identification signal to an internal virtual network signal. The translation is performed using a multi-stage lookup. The input signal is portioned into a plurality of subsets of bits. A first index to a first stage is provided by combining a portion of bits and a first delta subset of bits. A second index to a second stage is provided by combining data stored at the first index in the first stage and the a second delta subset of bits. The corresponding output signal is stored at the last index in the last stage. The use of the multi-stage lookup instead of a single-stage lookup reduces the memory required to perform the translation.
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公开(公告)号：US08867523B2
公开(公告)日：2014-10-21
申请号：US13692305
申请日：2012-12-03
发明人： Yehuda Binder
CPC分类号： H04L5/14 , H04B3/54 , H04B3/542 , H04B2203/5437 , H04B2203/5445 , H04B2203/545 , H04B2203/5458 , H04L12/2801 , H04L12/2803 , H04L12/2838 , H04L29/0602 , H04L43/00 , H04L2012/2843 , H04L2012/2845 , H04M19/02 , Y10S370/908
摘要： A serial intelligent cell (SIC) and a connection topology for local area networks using Electrically-conducting media. A local area network can be configured from a plurality of SIC's interconnected so that all communications between two adjacent SIC's is both point-to-point and bidirectional. Each SIC can be connected to one or more other SIC's to allow redundant communication paths. Communications in different areas of a SIC network are independent of one another, so that there is no fundamental limit on the size or extent of a SIC network. Each SIC can optionally be connected to one or more data terminals, computers, telephones, sensors, actuators, etc., to facilitate interconnectivity among such devices. Networks according to the present invention can be configured for a variety of applications, including a local telephone system, remote computer bus extender, multiplexers, PABX/PBX functionality, security systems, and local broadcasting services.
摘要翻译： 串行智能单元（SIC）和使用导电介质的局域网的连接拓扑。 可以从多个SIC互连的局域网配置局域网，使得两个相邻SIC之间的所有通信都是点到点和双向的。 每个SIC可以连接到一个或多个其他SIC以允许冗余通信路径。 SIC网络的不同区域的通信是相互独立的，所以对于SIC网络的规模或范围没有根本的限制。 每个SIC可以可选地连接到一个或多个数据终端，计算机，电话，传感器，致动器等，以便于这些设备之间的互连。 根据本发明的网络可以被配置用于各种应用，包括本地电话系统，远程计算机总线扩展器，复用器，PABX / PBX功能，安全系统和本地广播服务。
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公开(公告)号：US20040264621A1
公开(公告)日：2004-12-30
申请号：US10647664
申请日：2003-08-25
发明人： Tony Mai
IPC分类号： H03D003/24
CPC分类号： H03L7/10 , H03L7/0812 , H03L7/0891
摘要： An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.
摘要翻译： 延迟锁定环路中的初始化电路确保上电或其他复位时钟沿由相位检测器以适当的顺序以适当的顺序接收。 在延迟锁定环路复位之后，初始化电路确保在使相位检测器增加（或减小）延迟线中的延迟之前，接收到参考时钟的至少一个边沿。 在接收到反馈时钟的至少一个边缘之后，初始化电路使相位检测器能够减小（或增加）延迟线中的延迟。
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25.发明申请公开(公告)号：US20030179012A1
公开(公告)日：2003-09-25
申请号：US10395318
申请日：2003-03-21
IPC分类号： H03K019/094
CPC分类号： H04L5/1461
摘要： A circuit and method for accelerating bus line communication in an integrated circuit is disclosed. High speed transmission of signals along a bus line is achieved by driving a series of bus line segments with their own bi-directional bus amplification circuits. Because each bus line segment has less capacitive loading than longer non-segmented bus lines, voltage reversal, or data inversion of a pair of complementary lines of a bus line segment is accomplished at high speed. Each bi-directional bus amplification circuit includes a precharge circuit for precharging each complementary pair of lines to known logic levels, and a drive circuit for changing the logic level of each line. The bi-directional bus amplification circuit of the present invention logically connects two lines to each other while actively amplifying the signal in either direction without prior knowledge of which direction the signal must be driven, and without additional control overhead than that required for a conventional precharged bus line.
摘要翻译： 公开了一种用于加速集成电路中的总线通信的电路和方法。 通过用自己的双向总线放大电路驱动一系列总线线段，实现沿总线线路的信号的高速传输。 因为每个总线段具有比较长的非分段总线线路更少的电容负载，所以高速地实现总线线段的一对互补线的电压反转或数据反转。 每个双向总线放大电路包括预充电电路，用于将每条互补线对预充电到已知逻辑电平，以及用于改变每条线的逻辑电平的驱动电路。 本发明的双向总线放大电路逻辑上将两条线彼此逻辑地连接，同时在任一方向上主动放大信号，而不需要先前知道信号必须被驱动的方向，而不需要额外的控制开销，而不需要常规的预充电 公车线。
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26.发明申请公开(公告)号：US20030126113A1
公开(公告)日：2003-07-03
申请号：US10336055
申请日：2003-01-02
发明人： David A. Brown
IPC分类号： G06F007/00
CPC分类号： H04L45/742 , G06F17/30955 , G11C15/00 , H04L45/00 , H04L45/02 , H04L45/04 , H04L45/54 , H04L45/7453 , H04L45/7457 , Y10S707/99931 , Y10S707/99933 , Y10S707/99943
摘要： We present a lookup table which allows sparse subtree descriptors and dense subtree descriptors to be stored in the same memory. A subtree entry in the memory stores a dense subtree descriptor for a dense subtree or a plurality of sparse subtree descriptors for sparse subtrees. The subtree entry is indexed by a leaf in the previous subtree. The sparse subtree descriptor stores at least one node descriptor. The node descriptor describes a set of leaves in the sparse subtree having a common value. The common value is encoded in the node descriptor using run length encoding.
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27.发明申请Method and apparatus for an incremental update of a longest prefix match lookup table 有权用于增加更新最长前缀匹配查找表的方法和装置公开(公告)号：US20010043602A1
公开(公告)日：2001-11-22
申请号：US09733629
申请日：2000-12-08
发明人： David A. Brown
IPC分类号： H04L012/28
CPC分类号： H04L45/742 , G06F17/30955 , G11C15/00 , H04L45/00 , H04L45/02 , H04L45/04 , H04L45/54 , H04L45/7453 , H04L45/7457 , Y10S707/99931 , Y10S707/99933 , Y10S707/99943
摘要： A method and apparatus for performing an incremental update of a lookup table while the lookup table is available for searching is presented. To add or delete a route, a second set of routes is stored in a second memory space in the lookup table, while access is provided to the first set of routes stored in a first memory space in the lookup table. Access is provided to the first memory space through a first pointer stored in a subtree entry. After storing the second set of routes in the second memory space, access is switched to the first set of routes in the first memory space by replacing the first pointer stored in the subtree entry with a second pointer to the second memory space.
摘要翻译： 呈现在查找表可用于搜索时执行查找表的增量更新的方法和装置。 为了添加或删除路由，第二组路由被存储在查找表中的第二存储器空间中，而访问被提供给存储在查找表中的第一存储器空间中的第一组路由。 通过存储在子树条目中的第一个指针将访问提供给第一个存储空间。 在将第二组路由存储在第二存储器空间中之后，通过用存储在子树条目中的第一指针替换第二存储器空间的第二指针，将访问切换到第一存储器空间中的第一组路由。
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公开(公告)号：US20210368555A1
公开(公告)日：2021-11-25
申请号：US17311908
申请日：2019-12-18
发明人： Xuejun LU , Nima AHMADVAND
摘要： A network access system providing network access to a mobile terminal or other device via an untrusted access point such as a wireless access point in an untrusted network. The access point registers with a service gateway, and the wireless terminal connects with the access point and receives a first network address for use with the service gateway. The terminal registers with the service gateway via the access point, and a context identity is maintained at the service gateway, associating the terminal with the access point for the duration of the connection. The terminal can then access a wider network through the service gateway. The service gateway may maintain billing and reward data associated with the context identity.
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公开(公告)号：US20130215798A1
公开(公告)日：2013-08-22
申请号：US13692305
申请日：2012-12-03
发明人： Yehuda BINDER
IPC分类号： H04L5/14
CPC分类号： H04L5/14 , H04B3/54 , H04B3/542 , H04B2203/5437 , H04B2203/5445 , H04B2203/545 , H04B2203/5458 , H04L12/2801 , H04L12/2803 , H04L12/2838 , H04L29/0602 , H04L43/00 , H04L2012/2843 , H04L2012/2845 , H04M19/02 , Y10S370/908
摘要： A serial intelligent cell (SIC) and a connection topology for local area networks using Electrically-conducting media. A local area network can be configured from a plurality of SIC's interconnected so that all communications between two adjacent SIC's is both point-to-point and bidirectional. Each SIC can be connected to one or more other SIC's to allow redundant communication paths. Communications in different areas of a SIC network are independent of one another, so that there is no fundamental limit on the size or extent of a SIC network. Each SIC can optionally be connected to one or more data terminals, computers, telephones, sensors, actuators, etc., to facilitate interconnectivity among such devices. Networks according to the present invention can be configured for a variety of applications, including a local telephone system, remote computer bus extender, multiplexers, PABX/PBX functionality, security systems, and local broadcasting services.
摘要翻译： 串行智能单元（SIC）和使用导电介质的局域网的连接拓扑。 可以从多个SIC互连的局域网配置局域网，使得两个相邻SIC之间的所有通信都是点到点和双向的。 每个SIC可以连接到一个或多个其他SIC以允许冗余通信路径。 SIC网络的不同区域的通信是相互独立的，所以对于SIC网络的规模或范围没有根本的限制。 每个SIC可以可选地连接到一个或多个数据终端，计算机，电话，传感器，致动器等，以便于这些设备之间的互连。 根据本发明的网络可以被配置用于各种应用，包括本地电话系统，远程计算机总线扩展器，复用器，PABX / PBX功能，安全系统和本地广播服务。
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公开(公告)号：US20040123024A1
公开(公告)日：2004-06-24
申请号：US10386378
申请日：2003-03-10
发明人： Lawrence King
IPC分类号： G06F012/00
CPC分类号： H04L45/00 , G11C15/00 , H04L45/7453
摘要： A plurality of entities are stored in a single addressable location in a Content Addressable Memory (CAM). A column in a CAM entry is selected for storing an entity based on the property of the entity to distribute the entities among the columns to maximize memory utilization. A match for a search key stored in one of the plurality of columns can be found in a single search operation.
摘要翻译： 多个实体存储在内容可寻址存储器（CAM）中的单个可寻址位置中。 选择CAM条目中的列以基于实体的属性存储实体以在列之间分布实体以最大化内存利用率。 可以在单个搜索操作中找到存储在多个列之一中的搜索关键字的匹配。
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