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38 条记录 (耗时 0.025 秒)

    Wide frequency range delay locked loop
    2.
    发明申请
    Wide frequency range delay locked loop 有权
    宽频率范围延迟锁定环路

    公开(公告)号：US20040125905A1

    公开(公告)日：2004-07-01

    申请号：US10335535

    申请日：2002-12-31

    申请人： MOSAID Technologies, Inc.

    发明人： Peter Vlasenko ,  Dieter Haerle

    IPC分类号： H03D003/24

    CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

    摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

    摘要翻译： 延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。 该DLL结合了模拟域和数字域。 数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。 模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

    Dense mode coding scheme
    3.
    发明申请
    Dense mode coding scheme 有权
    密集模式编码方案

    公开(公告)号：US20040062208A1

    公开(公告)日：2004-04-01

    申请号：US10262643

    申请日：2002-09-30

    申请人： MOSAID Technologies Inc.

    发明人： David A. Brown ,  Peter B. Gillingham

    IPC分类号： H04L012/28

    CPC分类号： H04L45/00 ,  H04L45/7457

    摘要： A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key.

    摘要翻译： 公开了一种用于搜索密钥的最长前缀匹配的查找表。 查找表提供了单个搜索周期中的键的匹配。 通过将每个匹配存储在查找表中的一个位置来最大化存储在查找表中的匹配数。 二叉树被分成多个级别，每个级别具有多个子树。 为子树存储的子树描述符包含子树中每个节点的字段。 该字段的状态指示节点的条目是否存储在表中。 位向量允许为密钥存储的单个匹配索引。

    Method and apparatus for adaptive data compression
    4.
    发明申请
    Method and apparatus for adaptive data compression 有权

    公开(公告)号：US20030206125A1

    公开(公告)日：2003-11-06

    申请号：US10420018

    申请日：2003-04-18

    申请人： MOSAID Technologies, Inc.

    发明人： Mourad Abdat

    IPC分类号： H03M007/34

    CPC分类号： H03M7/3088

    摘要： We present a method and apparatus for performing adaptive data compression. An alphabet and vocabulary in the encoder and decoder is built adaptively and stored in a dictionary as symbols are to be encoded and decoded. Each time an unknown symbol is to be encoded by the encoder, the encoder adds the symbol to the dictionary and transmits it in plain in the encoded string. The code words transmitted by the encoder include symbols and indexes. The state of a prefix bit preceding the code word indicates whether the code word is a plain symbol or an index of a symbol or string of symbols stored in the dictionary. The decoder examines the prefix bit of each code word as it is received to determine if the code word stores a symbol in plain or in index. If the code word stores a symbol in plain, the decoder learns the symbol by adding a sequence of symbols resulting from the concatenation of previously decoded symbols and the first symbol of the currently decoded symbol and by adding the symbol to its dictionary. If the code word stores an index, the decoder decodes the code word by extracting the symbol or sequence of symbols stored in the dictionary at the respective index in the dictionary.

    Load balancing in IP address lookup
    5.
    发明申请
    Load balancing in IP address lookup 有权
    IP地址查找中的负载均衡

    公开(公告)号：US20020184221A1

    公开(公告)日：2002-12-05

    申请号：US10132675

    申请日：2002-04-24

    申请人： MOSAID Technologies, Inc.

    发明人： Imtiaz Ahmad ,  David A. Brown

    IPC分类号： G06F007/00 ,  G06F017/00

    CPC分类号： H04L45/745 ,  Y10S707/99933 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99956

    摘要： A load balancing mechanism maps a binary tree representation of a routing table into a set of fixed size memories. The mechanism efficiently utilizes the memory in the routing table without violating the tree precedence constraints and the memory access requirements of a pipelined system. The mechanism stores a subtree associated with a densely populated level of the binary tree in memory associated with lower levels.

    摘要翻译： 负载平衡机制将路由表的二叉树表示映射到一组固定大小的存储器中。 该机制有效地利用路由表中的存储器，而不违反流优先级约束和流水线系统的存储器访问要求。 该机制将与二进制树的密集层次相关联的子树存储在与较低级别相关联的存储器中。

    Method and apparatus for storing sparse and dense subtrees in a longest prefix match lookup table
    6.
    发明申请
    Method and apparatus for storing sparse and dense subtrees in a longest prefix match lookup table 有权
    用于在最长前缀匹配查找表中存储稀疏和密集子树的方法和装置

    公开(公告)号：US20010044876A1

    公开(公告)日：2001-11-22

    申请号：US09733761

    申请日：2000-12-08

    申请人： Mosaid Technologies, Inc.

    发明人： David A. Brown

    IPC分类号： G06F012/00

    CPC分类号： H04L45/742 ,  G06F17/30955 ,  G11C15/00 ,  H04L45/00 ,  H04L45/02 ,  H04L45/04 ,  H04L45/54 ,  H04L45/7453 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99943

    摘要： We present a lookup table which allows sparse subtree descriptors and dense subtree descriptors to be stored in the same memory. A subtree entry in the memory stores a dense subtree descriptor for a dense subtree or a plurality of sparse subtree descriptors for sparse subtrees. The subtree entry is indexed by a leaf in the previous subtree. The sparse subtree descriptor stores at least one node descriptor. The node descriptor describes a set of leaves in the sparse subtree having a common value. The common value is encoded in the node descriptor using run length encoding.

    摘要翻译： 我们提出一个查找表，允许稀疏子树描述符和密集子树描述符存储在同一个存储器中。 存储器中的子树条目存储密集子树的密集子树描述符或稀疏子树的多个稀疏子树描述符。 子树条目由先前子树中的叶子索引。 稀疏子树描述符存储至少一个节点描述符。 节点描述符描述具有公共值的稀疏子树中的一组叶。 公共值使用运行长度编码在节点描述符中编码。

    METHOD AND APPARATUS FOR STARTING AN INTERNAL COMBUSTION ENGINE
    8.
    发明申请
    METHOD AND APPARATUS FOR STARTING AN INTERNAL COMBUSTION ENGINE 有权
    用于启动内燃机的方法和装置

    公开(公告)号：US20130332055A1

    公开(公告)日：2013-12-12

    申请号：US13902088

    申请日：2013-05-24

    申请人： Mosaid Technologies Inc.

    发明人： Nicolas Bouchon ,  Martin Strange

    IPC分类号： F02N11/08

    CPC分类号： B60W20/40 ,  B60L2200/26 ,  B60L2240/423 ,  B60L2240/441 ,  B60L2240/445 ,  B60W10/06 ,  B60W10/08 ,  B60W20/00 ,  B60W2510/0638 ,  B60W2510/0676 ,  B60W2510/0685 ,  B60W2520/10 ,  B60W2710/083 ,  F02N11/04 ,  F02N11/08 ,  F02N11/0814 ,  F02N19/005 ,  F02N2019/007 ,  F02N2200/023 ,  F02N2300/104 ,  Y02T10/48 ,  Y02T10/6286 ,  Y02T10/642

    摘要： A method and apparatus for starting an internal combustion engine is disclosed. A motor is mechanically coupled to the engine, the engine having at least one moveable element mounted in a chamber, the moveable element being operable to cause a changing compression condition within the chamber and being mechanically coupled to a shaft for generating mechanical power. The method involves causing the motor to supply a positioning torque to the engine to move the at least one moveable element into a starting position. The method also involves causing the motor to supply a starting torque to the engine when the at least one moveable element is in the starting position to cause the moveable element to accelerate from the starting position under low compression conditions to generate sufficient momentum to overcome a peak compression condition in the chamber, thereby reducing the starting torque required to start the engine.

    摘要翻译： 公开了一种启动内燃机的方法和装置。 马达机械地联接到发动机，发动机具有安装在腔室中的至少一个可移动元件，该可移动元件可操作以在腔室内引起变化的压缩状态，并机械联接到轴以产生机械动力。 该方法涉及使马达向发动机提供定位扭矩以将至少一个可移动元件移动到起始位置。 该方法还涉及当至少一个可移动元件处于起始位置时使马达向发动机提供启动扭矩，以使可移动元件在低压缩条件下从起始位置加速以产生足够的动量以克服峰值 从而降低起动发动机所需的起动转矩。

    Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines
    9.
    发明申请
    Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines 有权
    用于高速和高能效微处理器管道的时钟逻辑多米诺骨架电路

    公开(公告)号：US20040164769A1

    公开(公告)日：2004-08-26

    申请号：US10730002

    申请日：2003-12-09

    申请人： Mosaid Technologies, Inc

    发明人： Raymond Jit-Hung Sung ,  Duncan George Elliott

    IPC分类号： H03K019/096

    CPC分类号： H03K19/0963

    摘要： A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.

    摘要翻译： 提供了一种用于单轨多米诺骨牌逻辑电路的系统方法，其中反相和非单调逻辑功能可以集成到几乎零开销的流水线系统中。 这种称为时钟逻辑（CL）-domino的逻辑系列功能完整，同时容忍偏差并最小化必须分配的时钟相位数。 在高偏移（1-FO4）条件下，1GHz下的CL-domino ALU的仿真结果显示，在双轨偏斜容忍多米诺骨牌逻辑中实现的相同ALU的功率降低了41％。 尽管在某些情况下还需要额外的设计工作，但是这种功率降低不会对双轨技术造成性能损失。

    Wide databus architecture
    10.
    发明申请
    Wide databus architecture 有权
    宽数据总线架构

    公开(公告)号：US20040136226A1

    公开(公告)日：2004-07-15

    申请号：US10691111

    申请日：2003-10-22

    申请人： MOSAID Technologies Inc.

    发明人： Richard C. Foss

    IPC分类号： G11C011/24

    CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

    摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

    摘要翻译： 具有位线对的动态随机存取存储器（DRAM），每对都连接到第一位线读出放大器，与形成阵列的位线对交叉的字线，连接到位线的电荷存储单元，每个具有连接到位线的使能输入 字线，位线读出放大器以二维阵列连接，成对的初级数据总线通过第一存取晶体管连接到阵列的每一行中的多个相应的位线读出放大器，用于使第一存取晶体管的列，数据总线 读出放大器各自连接到对应的数据总线对，辅助数据总线，次级数据总线通过第二存取晶体管连接到数据总线读出放大器，以及用于使能第二存取晶体管的装置，由此每个主数据总线对可以被多个 阵列的相应行中的读出放大器和辅助数据总线可以由多个pri共享 玛丽数据总线对。