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    Zero overhead block floating point implementation in CPU's
    21.
    发明授权
    Zero overhead block floating point implementation in CPU's 有权
    CPU中的零开销块浮点实现

    公开(公告)号：US08788549B2

    公开(公告)日：2014-07-22

    申请号：US13461902

    申请日：2012-05-02

    申请人： Gururaj Padaki ,  Anindya Saha ,  Parag Naik ,  Vishwakumara Kayargadde ,  Sunil Hr

    发明人： Gururaj Padaki ,  Anindya Saha ,  Parag Naik ,  Vishwakumara Kayargadde ,  Sunil Hr

    IPC分类号： G06F7/00 ,  G06F7/38 ,  G06F7/483

    CPC分类号： G06F7/483

    摘要： A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

    摘要翻译： 提供了一种用于通过检测中央处理单元中的输入信号的动态范围来计算块浮点缩放因子的系统，而没有额外的开销周期。 该系统包括动态范围监测单元，其通过窥探输出写入数据和输入信号的输入存储器读取数据来检测输入信号的动态范围。 动态范围监视单元包括运行的最大计数单元，其存储前导零和前导零的计数的最小值，以及存储尾随零计数的最小值的运行最小计数。 基于前导零和前导零的计数的最小值和尾随零的计数来检测动态范围。 该系统还包括一个缩放因子计算模块，它根据动态范围计算块浮点（BFP）缩放因子。

    Digital Filter Implementation for Exploiting Statistical Properties of Signal and Coefficients
    23.
    发明申请
    Digital Filter Implementation for Exploiting Statistical Properties of Signal and Coefficients 有权
    数字滤波器实现信号和系数的统计特性

    公开(公告)号：US20120284318A1

    公开(公告)日：2012-11-08

    申请号：US13462116

    申请日：2012-05-02

    申请人： Parag NAIK ,  Anindya SAHA ,  Gururaj PADAKI ,  Subrahmanya Kondageri SHANKARAIAH ,  Saurabh MISHRA

    发明人： Parag NAIK ,  Anindya SAHA ,  Gururaj PADAKI ,  Subrahmanya Kondageri SHANKARAIAH ,  Saurabh MISHRA

    IPC分类号： G06F17/10

    CPC分类号： H03H21/0012 ,  H03H2021/007 ,  H03H2021/0072 ,  H03H2218/10

    摘要： A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

    摘要翻译： 提供一种实现数字滤波器的方法。 该方法包括（a）通过测量输入数据样本的前导零或一个之间的距离以及输入数据样本的尾随零来确定输入信号的输入数据样本的位宽。 输入数据样本是通过以预定义的时间间隔对输入信号进行采样而获得的，（b）基于输入数据样本的位宽的第一概率分布函数（PDF））获得具有可变位宽的位宽乘数 ，（c）基于输入数据样本的位宽和滤波器系数的位宽分配输入数据样本和滤波器系数到位宽乘法器的一个位宽倍数，以及（d） 在一个位宽乘数上执行乘法和累加（MAC）运算的乘法运算，以产生数字滤波器的输出。

    REDUCING POWER CONSUMPTION OF A MICROPROCESSOR
    24.
    发明申请
    REDUCING POWER CONSUMPTION OF A MICROPROCESSOR 有权
    降低微处理器的功耗

    公开(公告)号：US20090177902A1

    公开(公告)日：2009-07-09

    申请号：US12335137

    申请日：2008-12-15

    申请人： Parag Naik

    发明人： Parag Naik

    IPC分类号： G06F1/32 ,  G06F9/30

    CPC分类号： G06F1/32 ,  G06F9/30

    摘要： Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence are assigned operation codes that require fewer signal transitions. As a result, the power consumption of the microprocessor is reduced.

    摘要翻译： 方法和设备，包括计算机程序产品，实现和使用技术来降低微处理器的功耗。 对微处理器的指令集中的一个或多个信号转换进行分析。 发生概率分配给指令集中的每个指令。 基于指令的出现概率，将二进制操作码分配给每个指令。 具有最高出现概率的指令被分配为需要较少信号转换的操作代码。 结果，微处理器的功耗降低了。