公开(公告)号：US06564364B1

公开(公告)日：2003-05-13

申请号：US09909354

申请日：2001-07-18

申请人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

发明人： Peter Dahl ,  Byron Dickinson ,  Margie Levine ,  Paul Rodman

IPC分类号： G06F9455

CPC分类号： G06F17/5068

摘要： A method for implementing a user interface for performing physical design operations on an integrated circuit netlist. The method includes accessing an input file and parsing the input file to identify elements within the netlist matching corresponding elements within a first library file. At least one element within the netlist is identified that does not have a corresponding element within the first library file. A modifiable element corresponding to the at least one element is stored within a second library file. A subsequent occurrence of the at least one element is matched to the modifiable element in the second library file. The parsing of the input file of the integrated circuit netlist is completed and a build of the integrated circuit netlist is then completed based on the parsed input file and specifications stored in the first or second library files.

摘要翻译： 一种用于实现用于在集成电路网表上执行物理设计操作的用户界面的方法。 该方法包括访问输入文件并解析输入文件以识别与第一库文件内的相应元素匹配的网表内的元素。 网表中至少有一个元素在第一个库文件中没有相应的元素。 对应于至少一个元素的可修改元素被存储在第二库文件中。 随后发生的至少一个元素与第二库文件中的可修改元素相匹配。 完成集成电路网表的输入文件的解析，然后基于解析的输入文件和存储在第一或第二库文件中的规范，完成集成电路网表的构建。

公开(公告)号：US5954815A

公开(公告)日：1999-09-21

申请号：US781851

申请日：1997-01-10

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

摘要翻译： 一种计算系统，包括包括存储多条指令的多行的指令存储器和存储多个分支预测条目的分支存储器的装置，每个分支预测条目包含用于预测由a 当执行分支指令时，将采用存储在指令存储器中的分支指令。 每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段， 以及指示分支指令在与目标地址对应的行内位于何处的源字段。 计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。 当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出， 在包含分支指令的行后立即进入管道。 无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。