公开(公告)号：US06247124B1

公开(公告)日：2001-06-12

申请号：US09363635

申请日：1999-07-30

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F932

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

摘要翻译： 计算系统包括具有存储多条指令的多行的指令存储器的装置，以及存储多个分支预测条目的分支存储器，每个分支预测条目包含用于预测分支指定的分支 存储在指令存储器中的指令将在执行分支指令时进行。 每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段， 以及指示分支指令在与目标地址对应的行内位于何处的源字段。 计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。 当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出， 在包含分支指令的行后立即进入管道。 无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。

公开(公告)号：US06691221B2

公开(公告)日：2004-02-10

申请号：US09863898

申请日：2001-05-24

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F938

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. The instruction loading circuit loads the L instructions from the second instruction storing circuit into the positions previously occupied by the L instructions dispatched from the first instruction storing circuit. A feedback path is also provided to reload an instruction not previously dispatched.

摘要翻译： 计算系统具有第一和第二指令存储电路，每个指令存储电路存储用于并行输出的N个指令。 耦合到第一指令存储电路的指令调度电路调度存储在第一指令存储电路中的L指令，其中L小于或等于N.一个指令加载电路，耦合到指令调度电路和第一和第二指令 指令存储电路，在从第一指令存储电路发出L指令之后并且从第一指令存储电路调度进一步的指令之前，将来自第二指令存储电路的L指令加载到第一指令存储电路中。 指令加载电路将来自第二指令存储电路的L指令加载到先前由从第一指令存储电路分派的L指令占据的位置。 还提供反馈路径来重新加载先前未发送的指令。

公开(公告)号：US5604909A

公开(公告)日：1997-02-18

申请号：US168744

申请日：1993-12-15

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.

摘要翻译： 计算系统具有第一和第二指令存储电路，每个指令存储电路存储用于并行输出的N个指令。 耦合到第一指令存储电路的指令调度电路调度存储在第一指令存储电路中的L指令，其中L小于或等于N.一个指令加载电路，耦合到指令调度电路和第一和第二指令 指令存储电路，在从第一指令存储电路发出L指令之后并且从第一指令存储电路调度进一步的指令之前，将来自第二指令存储电路的L指令加载到第一指令存储电路中。 还提供了用于绕过第二指令存储电路的旁路电路。

公开(公告)号：US5537538A

公开(公告)日：1996-07-16

申请号：US166969

申请日：1993-12-15

申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  Chandra S. Joshi ,  William A. Huffman ,  Monica R. Nofal ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang

发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  Chandra S. Joshi ,  William A. Huffman ,  Monica R. Nofal ,  Paul Rodman ,  Joseph T. Scanlon ,  Man K. Tang

IPC分类号： D06M13/46 ,  C11D1/04 ,  C11D1/62 ,  C11D1/645 ,  C11D1/65 ,  C11D1/72 ,  C11D1/835 ,  C11D3/00 ,  D06M20060101 ,  D06M13/02 ,  D06M13/184 ,  D06M13/188 ,  D06M13/322 ,  D06M13/463 ,  G06F9/38 ,  G06F11/36 ,  G06F11/34 ,  G06F9/30

CPC分类号： G06F11/3664 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

摘要： A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

摘要翻译： 处理器系统，可在正常操作模式之间切换，无需精确的浮点异常，以及具有精确浮点异常的调试操作模式。 处理器系统包括调度整数和浮点指令的调度，具有用于执行整数指令的多级整数流水线的整数单元，以及具有用于执行浮点指令的多级浮点流水线的浮点单元。 系统在正常模式下开始运行，并且在接收到“切换到调试模式”的指令时，处理器切换到调试操作模式，具有精确的例外。 在调试模式下，一旦调度了浮点指令，就会阻止所有其他指令被提交，直到系统确定浮点指令是否产生异常。 因此，允许系统在不处于正常模式时发出精确异常。

公开(公告)号：US5954815A

公开(公告)日：1999-09-21

申请号：US781851

申请日：1997-01-10

申请人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

发明人： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

摘要： A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction. An invalidate circuit invalidates any instructions following the branch instruction in the line containing the branch instruction and prior to the target instruction in the line containing the target instruction.

摘要翻译： 一种计算系统，包括包括存储多条指令的多行的指令存储器和存储多个分支预测条目的分支存储器的装置，每个分支预测条目包含用于预测由a 当执行分支指令时，将采用存储在指令存储器中的分支指令。 每个分支预测条目包括用于指示包含要执行的目标指令的行的目标地址的分支目标字段，如果分支被采用，则指示目标指令位于由分支目标地址指示的行内的目的地字段， 以及指示分支指令在与目标地址对应的行内位于何处的源字段。 计数器存储用于寻址指令存储器的地址值，并且递增电路递增计数器中的地址值，以便在正常顺序操作期间顺序寻址指令存储器中的行。 当分支预测条目预测在执行分支指令时，将采用存储在指令存储器中的分支指令指定的分支，计数器加载电路将目标地址加载到计数器中，导致包含目标指令的行被取出， 在包含分支指令的行后立即进入管道。 无效电路使包含分支指令的行中的分支指令之后的指令和包含目标指令的行中的目标指令之前的任何指令无效。