Abstract:
An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.
Abstract:
A high-density plasma method is provided for forming a SiOXNY thin-film. The method provides a substrate and introduces a silicon (Si) precursor. A thin-film is deposited overlying the substrate, using a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, a SiOXNY thin-film is formed, where (X+Y 0). The SiOXNY thin-film can be stoichiometric or non-stoichiometric. The SiOXNY thin-film can be graded, meaning the values of X and Y vary with the thickness of the SiOXNY thin-film. Further, the process enables the in-situ deposition of a SiOXNY thin-film multilayer structure, where the different layers may be stoichiometric, non-stoichiometric, graded, and combinations of the above-mentioned types of SiOXNY thin-films.
Abstract:
A deposition oxide interface with improved oxygen bonding and a method for bonding oxygen in an oxide layer are provided. The method includes depositing an M oxide layer where M is a first element selected from a group including elements chemically defined as a solid and having an oxidation state in a range of +2 to +5, plasma oxidizing the M oxide layer at a temperature of less than 400° C. using a high density plasma source, and in response to plasma oxidizing the M oxide layer, improving M-oxygen bonding in the M oxide layer. The plasma oxidation process diffuses excited oxygen radicals into the oxide layer. The plasma oxidation is performed at specified parameters including temperature, power density, pressure, process gas composition, and process gas flow. In some aspects of the method, M is silicon, and the oxide interface is incorporated into a thin film transistor.
Abstract:
A silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device and associated fabrication process are presented. The method provides a substrate bottom electrode, and forms a plurality of Si nanocrystal embedded SiOx film layers overlying the bottom electrode, where X is less than 2. Each SiOx film layer has a Si excess concentration in a range of about 5 to 30%. The outside film layers sandwich an inner film layer having a lower concentration of Si nanocrystals. Alternately stated, the outside Si nanocrystal embedded SiOx film layers have a higher electrical conductivity than a sandwiched inner film layer. A transparent top electrode is formed over the plurality of Si nanocrystal embedded SiOx film layers. The plurality of Si nanocrystal embedded SiOx film layers are deposited using a high density plasma-enhanced chemical vapor deposition (HD PECVD) process. The HD PECVD process initially deposits SiOx film layers, which are subsequently annealed.
Abstract:
A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.
Abstract:
A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having a thickness in a range of 30 to 200 nanometers (nm). For example, the film may be SiOx, where X is less than 2, Si3Nx, where X is less than 4, or SiCx, where X is less than 1. The Si insulating film is annealed, and as a result, Si nanocrystals are formed in the film. Then, a transparent metal electrode is formed overlying the Si insulator film. An annealed Si nanocrystalline SiOx film has a turn-on voltage of less than 20 volts, as defined with respect to a surface emission power of greater than 0.03 watt per square meter.
Abstract:
A pixel-by-pixel, digitally-addressable, pixelated, precursor, fluid-assay, active-matrix micro-structure including plural pixels formed on a substrate, wherein each pixel includes (a) at least one non-functionalized, digitally-addressable assay sensor, and (b), disposed operatively adjacent this sensor, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the at least one assay sensor, an ambient electromagnetic field environment which is structured to assist in functionalizing, as a possession on said at least one assay sensor, at least one digitally-addressable assay site which will display an affinity for a selected fluid-assay material.
Abstract:
A mobile satellite communication system is provided to control the transfer of a terminal for a single-hop call from at least one of a clear mode and a ciphered mode with respect to a gateway station to a ciphered mode with respect to a satellite link connecting the terminal with another terminal for a single-hop, terminal-to-terminal call using a cipher key and an encryption algorithm common to the terminal and the other terminal. Frame number offset data, which indicates a mapping delay between received and transmitted time slots at the satellite, is provided to both terminals in a terminal-to-terminal call for ciphering synchronization.
Abstract:
An MSAT system is provided which optimizes satellite resources when implementing a single-hop TtT call. The system allocates satellite channels and signaling channels for a single-hop TtT call to the participating terminals at an early stage during the call set-up procedure such that only a single pair of satellite channels are assigned to each of the terminals for call establishment and for use during the call, as opposed to two pairs of satellite channels. A test message for signaling channel (e.g., TTCH) validation is transmitted from the network (e.g., from a gateway station controller) to each of the terminals.
Abstract:
A mobile satellite (MSAT) system is provided for establishing a single-hop terminal-to-terminal call between two terminals. The MSAT system maintains a signaling path between each terminal and a gateway station during the terminal-to-terminal call although a call path between the mobile switching center and the originating terminal is blocked by the satellite. During single-hop call establishment, satellite channels for the terminal-to-terminal call path and for signaling are allocated. The allocated channels are assigned when a direct satellite link for the terminal-to-terminal call is established; otherwise, the call can proceed as a double-hop call using previously assigned satellite channels. A verification signal is sent on the direct satellite link which is for processing by the terminals and which contains information that causes the signal to be ignored by a gateway station. During a single-hop terminal-to-terminal call, signaling from a destination gateway station to an originating terminal at another gateway station is sent via an intranetwork communication system connecting traffic control subsystems in different gateway stations and the satellite channels allocated to the originating terminal