公开(公告)号：US06334176B1

公开(公告)日：2001-12-25

申请号：US09062152

申请日：1998-04-17

Applicant: Hunter Ledbetter Scales, III ,  Keith Everett Diefendorff ,  Brett Olsson ,  Pradeep Kumar Dubey ,  Ronald Ray Hochsprung

Inventor： Hunter Ledbetter Scales, III ,  Keith Everett Diefendorff ,  Brett Olsson ,  Pradeep Kumar Dubey ,  Ronald Ray Hochsprung

IPC: G06F1500

CPC classification number: G06F9/30043 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3816 ,  G06F17/16

Abstract: The data processing system loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The control vector is specified by calculating the offset of a selected vector element of the input vector relative to a base address of the input vector and loading each element with an index equal to the relative offset. Alternatively, the generation of the alignment vector is made by performing a look-up within a look-up table. For additional loads from the same vector, the control vector does not change, since the alignment shift amount of the vector from an address boundary does not change. A permutation instruction can then be executed to load and shift the data to realign it in the output register at the vector boundary.

Abstract translation: 数据处理系统将三个输入操作数，包括两个输入向量和一个控制向量加载到向量寄存器中，并执行由控制向量指定的两个输入向量的置换，并将该操作的结果作为输出操作数存储在 输出寄存器。 控制向量包括十六个索引，每个索引唯一地标识输入寄存器中的任一个输入数据的单个字节，并且可以在操作代码中指定，或者是先前在向量寄存器内执行的计算的结果。 控制向量通过计算输入向量的选定向量元素相对于输入向量的基址的偏移量来指定，并以等于相对偏移的索引加载每个元素。 或者，通过在查找表内执行查找来进行对齐向量的生成。 对于来自相同向量的额外负载，控制向量不改变，因为来自地址边界的向量的对准移位量不改变。 然后可以执行置换指令以加载和移位数据以在向量边界处的输出寄存器中重新对准它。

公开(公告)号：US06246777B1

公开(公告)日：2001-06-12

申请号：US09273055

申请日：1999-03-19

Applicant: Saurabh Agarwal ,  Alok Aggarwal ,  Harpal Singh Bassali ,  Jatin Chhugani ,  Pradeep Kumar Dubey

Inventor： Saurabh Agarwal ,  Alok Aggarwal ,  Harpal Singh Bassali ,  Jatin Chhugani ,  Pradeep Kumar Dubey

IPC: G06K900

CPC classification number: G06T1/0057 ,  G06T2201/0051

Abstract: A verification system for still images that embeds a watermark so that no visual artifacts are created in the images and thus maintains the visual quality of the image. The algorithm embeds information in an uncompressed image so as to later detect the alteration of the image, as well as the location of the alteration. The embedding of information into a source image is based on a defined mapping process. An image plane consists of macroblocks, which are themselves comprised of microblocks. A code is embedded corresponding to the value of this image property in each macroblock. The specific sequence of microblocks used for embedding this information in the watermarking image plane is a unique function of this property for the corresponding set of microblocks in the indexing image plane. This information can be later decoded from the stamped image. The watermark is embedded by combining the pixel values of the image with the watermark. The watermark is altered if the image is altered.

Abstract translation: 用于嵌入水印的静止图像的验证系统，使得在图像中不产生视觉伪影，从而保持图像的视觉质量。 该算法将信息嵌入到未压缩图像中，以便稍后检测图像的改变以及改变的位置。 将信息嵌入到源图像中是基于定义的映射过程。 图像平面由宏块组成，宏块本身由微块组成。 在每个宏块中嵌入与该图像属性的值相对应的代码。 用于将该信息嵌入水印图像平面中的微块的特定序列是该索引图像平面中相应的微块集合的该属性的唯一函数。 该信息可以稍后从加盖的图像中解码。 通过将图像的像素值与水印相结合来嵌入水印。 如果图像被改变，则改变水印。

公开(公告)号：US5809566A

公开(公告)日：1998-09-15

申请号：US702407

申请日：1996-08-14

Applicant: Mark Jay Charney ,  Pradeep Kumar Dubey ,  Thomas Robert Puzak ,  William John Starke

Inventor： Mark Jay Charney ,  Pradeep Kumar Dubey ,  Thomas Robert Puzak ,  William John Starke

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3806 ,  G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/3802 ,  G06F9/383 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Dynamic migration of a cache prefetch request is performed. A prefetch candidate table maintains at least one prefetch candidate which may be executed as a prefetch request. The prefetch candidate includes one or more trigger addresses which correspond to locations in the instruction stream where the prefetch candidate is to be executed as a prefetch request. A jump history table maintains a record of target addresses of program branches which have been executed. The trigger addresses in the prefetch candidate are defined by the target addresses of recently executed program branches maintained in the jump history table. A pending prefetch table maintains a record of executed prefetch requests. When an operation such as a cache miss, cache hit, touch instruction or program branch is identified, the pending prefetch table is scanned to determine whether a prefetch request has been executed. If a prefetch request has been executed, the prefetch candidate which was used to execute that prefetch request is updated. That is, a new trigger address in the prefetch candidate is selected in order to reduce access latency.

Abstract translation: 执行缓存预取请求的动态迁移。 预取候选表维持至少一个可以作为预取请求执行的预取候选。 预取候选包括一个或多个触发地址，其对应于将作为预取请求执行预取候选的指令流中的位置。 跳转历史记录表维护已执行的程序分支的目标地址记录。 预取候选中的触发地址由保持在跳转历史表中的最近执行的程序分支的目标地址定义。 待处理的预取表维护执行的预取请求的记录。 当识别诸如高速缓存未命中，缓存命中，触摸指令或程序分支的操作​​时，扫描挂起的预取表以确定是否已经执行了预取请求。 如果已经执行了预取请求，则更新用于执行该预取请求的预取候选。 也就是说，选择预取候选中的新的触发地址以便减少访问延迟。

公开(公告)号：US5761515A

公开(公告)日：1998-06-02

申请号：US616131

申请日：1996-03-14

Applicant: Charles Marshall Barton, III ,  Pradeep Kumar Dubey ,  Jaime Humberto Moreno

Inventor： Charles Marshall Barton, III ,  Pradeep Kumar Dubey ,  Jaime Humberto Moreno

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/45 ,  G06F12/00

CPC classification number: G06F8/4442 ,  G06F9/30047 ,  G06F9/322 ,  G06F9/383

Abstract: In a computer system having a hierarchical memory, the problem of tolerating cache miss latency is solved by dynamically switching appropriately between two different code sequences, one optimized at compile-time, assuming a cache-hit, and the other optimized at compile-time, assuming a cache-miss. A method for processing instructions and data in a computer system including a hierarchical memory and a static instruction sequence including a memory access instruction and associated memory access latency specific code sequences, each code sequence optimized dependent on an execution of the memory access instruction causing one of a hit or a miss at a level of the memory hierarchy, includes the steps of: decoding and executing the memory access instruction and storing information indicating whether the execution of the memory access instruction caused the hit or the miss; and branching to a cache hit optimized code sequence when the information indicates the hit and a miss optimized code sequence when the information indicates the miss, responsive to the step of storing. Preferably, the memory access latency specific code sequences are associated with one or more identified critical miss-points. The step of branching may be responsive to an inserted branch instruction associated with the memory access instruction. The branch instruction may also specify a level of the cache memory upon which the step of branching is recommended.

Abstract translation: 在具有分层存储器的计算机系统中，容忍高速缓存未命中延迟的问题通过在两个不同的代码序列之间动态地切换来解决，一个在编译时优化，假设一个高速缓存命中，另一个在编译时被优化， 假设缓存未命中。 一种用于处理计算机系统中的指令和数据的方法，包括分层存储器和静态指令序列，所述分层存储器和静态指令序列包括存储器访问指令和相关联的存储访问延迟特定代码序列，每个代码序列根据存储器存取指令的执行而优化， 包括以下步骤：解码和执行存储器访问指令并存储指示存储器访问指令的执行是否导致命中或错过的信息; 并且当所述信息指示所述命中时，并且当所述信息指示所述遗漏时，分支到高速缓存命中优化代码序列，并响应于所述存储步骤。 优选地，存储器访问等待时间特定代码序列与一个或多个识别的关键错误点相关联。 分支的步骤可以响应于与存储器访问指令相关联的插入的分支指令。 分支指令还可以指定推荐分支步骤的缓存存储器的级别。