Branch target address cache storing two or more branch target addresses per index
    22.
    发明申请
    Branch target address cache storing two or more branch target addresses per index 审中-公开
    分支目标地址缓存,每个索引存储两个或更多个分支目标地址

    公开(公告)号:US20060218385A1

    公开(公告)日:2006-09-28

    申请号:US11089072

    申请日:2005-03-23

    IPC分类号: G06F9/00

    CPC分类号: G06F9/3806 G06F9/3848

    摘要: A Branch Target Address Cache (BTAC) stores at least two branch target addresses in each cache line. The BTAC is indexed by a truncated branch instruction address. An offset obtained from a branch prediction offset table determines which of the branch target addresses is taken as the predicted branch target address. The offset table may be indexed in several ways, including by a branch history, by a hash of a branch history and part of the branch instruction address, by a gshare value, randomly, in a round-robin order, or other methods.

    摘要翻译: 分支目标地址缓存(BTAC)在每个高速缓存行中存储至少两个分支目标地址。 BTAC由截断的分支指令地址索引。 从分支预测偏移表获得的偏移确定哪个分支目标地址被采用为预测分支目标地址。 偏移表可以通过分支历史,分支历史和部分分支指令地址的散列,以循环次序或其他方法随机的gshare值被索引。

    Versatile resource computer-based training system
    23.
    发明授权
    Versatile resource computer-based training system 失效
    多功能资源计算机培训系统

    公开(公告)号:US07043193B1

    公开(公告)日:2006-05-09

    申请号:US09638771

    申请日:2000-08-15

    IPC分类号: G09B11/00

    CPC分类号: G09B7/00

    摘要: A computer-based training (CBT) system using versatile resources to support multiple training scenarios in a multi-user environment. The CBT system includes an authoring program module accessible by a lesson designer to create a number of lessons. The CBT system includes one or more runner program modules accessible by lesson takers for running the lessons created with the authoring program module. The CBT system also includes a relational database accessible by the runner program modules and comprises administrative information and information for retrieving desired resources. The versatile resources of the present invention reduce the memory storage requirements for a CBT system capable of supporting multiple training scenarios in a multi-user network environment. The CBT system realistically simulates multi-mode communication systems and implements progressive mentoring and voice-based progression methodologies.

    摘要翻译: 基于计算机的培训(CBT)系统使用多功能资源来支持多用户环境中的多种训练场景。 CBT系统包括创作程序模块,可由课程设计人员访问,以创建一些课程。 CBT系统包括一个或多个赛跑者程序模块,可由课程人员访问,用于运行通过创作程序模块创建的课程。 CBT系统还包括可由赛跑者程序模块访问的关系数据库,并包括用于检索所需资源的管理信息和信息。 本发明的多功能资源减少了能够在多用户网络环境中支持多种训练场景的CBT系统的存储器存储要求。 CBT系统实际模拟多模式通信系统,并实施逐步的指导和基于语音的进步方法。

    Cheese ripening process
    24.
    发明授权
    Cheese ripening process 失效
    奶酪成熟过程

    公开(公告)号:US06955828B2

    公开(公告)日:2005-10-18

    申请号:US10168581

    申请日:2000-12-22

    申请人: Mark Rodney Smith

    发明人: Mark Rodney Smith

    CPC分类号: A23C19/0323 A23C19/0682

    摘要: Methods for accelerated cheese ripening using a biological agent, in particular microorganisms, wherein the biological agent has been treated with a surface active agent, (e.g. a detergent or surfactant) and wherein the biological agent is not an attenuated bacterial starter culture.

    摘要翻译: 使用生物制剂加速干酪熟化的方法,特别是微生物,其中生物制剂已用表面活性剂(例如洗涤剂或表面活性剂)处理,并且其中生物制剂不是减毒的细菌起始培养物。

    Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes
    25.
    发明申请
    Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes 失效
    翻译看起来缓冲区(TLB)具有增加的多线程计算机进程的平移能力

    公开(公告)号:US20050108497A1

    公开(公告)日:2005-05-19

    申请号:US10714282

    申请日:2003-11-14

    摘要: Method and apparatus for increasing the number of real memory addresses accessible through a translational look-aside buffer (TLB) by a multi thread CPU. The buffer entries include a virtual address, a real address and a special mode bit indicating whether the address represents one of a plurality of threads being processed by the CPU. If the special mode bit is set, the real address associated with the virtual address higher order bits are concatenated with the thread identification number being processed to obtain a real address. Buffer entries containing no special mode bit, or special mode bit set to 0, are processed by using the full length of the real address associated with the virtual address stored in the look-aside buffer (TLB).

    摘要翻译: 用于通过多线程CPU通过翻译后备缓冲器(TLB)来访问的实际存储器地址的数量的方法和装置。 缓冲器条目包括虚地址,实地址和特殊模式位,指示地址是否表示CPU正在处理的多个线程中的一个。 如果设置了特殊模式位,则与虚拟地址较高位相关联的实际地址与被处理的线程标识号连接以获得实际地址。 通过使用与存储在后备缓冲区(TLB)中的虚拟地址相关联的实际地址的全长处理不包含特殊模式位或特殊模式位设置为0的缓冲区条目。

    Speculative instruction issue in a simultaneously multithreaded processor
    26.
    发明申请
    Speculative instruction issue in a simultaneously multithreaded processor 失效
    同时多线程处理器中的推测性指令问题

    公开(公告)号:US20050060518A1

    公开(公告)日:2005-03-17

    申请号:US10664384

    申请日:2003-09-17

    IPC分类号: G06F9/30 G06F9/38

    摘要: A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

    摘要翻译: 一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。 在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。 指令问题逻辑根据当指令到达需要的流水线中的阶段时,基于所需操作数将可用的概率来推测来自给定线程的指令。 如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率,则指令的发出被阻止。 一旦指令停顿的概率低于某个阈值,则根据当前流水线条件,允许发出指令。

    METHOD AND APPARATUS FOR IDENTIFYING WIRELESS ACCESS POINTS USING BEACON FRAMES
    27.
    发明申请
    METHOD AND APPARATUS FOR IDENTIFYING WIRELESS ACCESS POINTS USING BEACON FRAMES 有权
    使用BEACON框架识别无线接入点的方法和设备

    公开(公告)号:US20130170432A1

    公开(公告)日:2013-07-04

    申请号:US13343574

    申请日:2012-01-04

    IPC分类号: H04W4/00

    摘要: Techniques are described for identifying a wireless access point device using beacon messages and probe responses. An access point may generate and broadcast beacon messages which include an information element containing information specific to the device as well as to the current context of the device. For example, the information element may include a device vendor ID, product ID, and a device-unique ID. That is, the information element provides information related to the device itself independently from the configuration of the wireless network which the beacon message (or probe response) is associated with.

    摘要翻译: 描述了使用信标消息和探测响应来识别无线接入点设备的技术。 接入点可以生成和广播信标消息,其包括信息元素,该信息元素包含该设备特有的信息以及该设备的当前上下文。 例如,信息元素可以包括设备供应商ID,产品ID和设备唯一ID。 也就是说,信息元素独立于信标消息(或探测响应)相关联的无线网络的配置提供与设备本身相关的信息。

    Wall panel with extended integral post
    28.
    发明授权
    Wall panel with extended integral post 有权
    墙面板与扩展整体柱

    公开(公告)号:US08407956B2

    公开(公告)日:2013-04-02

    申请号:US12883476

    申请日:2010-09-16

    申请人: Rodney Smith

    发明人: Rodney Smith

    IPC分类号: E04D27/10 E04B1/04

    CPC分类号: E02D29/02

    摘要: A wall module for a modular wall structure integrates a wall panel portion with a post portion having top or upper and bottom or lower extensions and at least one groove for receiving a distal end of a wall panel portion of an adjacent module. The bottom/lower extension is set within an exposed portion of a reinforcing cage of a caisson or pier extending below grade and encapsulated with a material such as concrete to integrate the caisson or pier with the bottom/lower post extension. Integration of the caisson or pier with the module provides numerous economies of transportation, construction and repair and improved safety. The top/upper post extension is of a length to accommodate the full height of the wall panel portion of an adjacent module to improve strength and stability of the modular wall.

    摘要翻译: 用于模块化壁结构的壁模块将壁板部分与具有顶部或上部和底部或底部延伸部的柱部分以及用于接收相邻模块的壁板部分的远端的至少一个凹槽相结合。 底部/下部延伸部设置在下沉级别的沉箱或码头的加强笼的暴露部分内,并用诸如混凝土的材料包住以将沉箱或码头与底部/下部柱延伸部整合。 沉箱或码头与模块的整合提供了许多运输,施工和维修经验,并提高了安全性。 顶部/上部柱延伸部分具有适应相邻模块的壁板部分的全部高度的长度,以提高模块化壁的强度和稳定性。

    Real-time blog interaction
    29.
    发明授权
    Real-time blog interaction 失效
    实时博客互动

    公开(公告)号:US07933958B2

    公开(公告)日:2011-04-26

    申请号:US10863324

    申请日:2004-06-08

    IPC分类号: G06F15/16

    摘要: The present invention is a system, method and apparatus for for real-time blogging. In a preferred aspect of the invention, a real-time bi-directional blogging system can include a blog and a bi-directional syndication interface to the blog. Importantly, an instant messaging system can be coupled to the syndication interface of the blog. The instant messaging system of the present invention can include a chat server and at least one chat client. Notably, a bot can be coupled to the chat server. The bot can be programmed to communicate blog postings received in the chat server to the chat client or clients. The bot can be further programmed to communicate responses to the blog postings received from the chat client or clients to the blog through the syndication interface.

    摘要翻译: 本发明是用于实时博客的系统,方法和装置。 在本发明的优选方面,实时双向博客系统可以包括博客和博客的双向联合接口。 重要的是,即时消息系统可以耦合到博客的联合接口。 本发明的即时消息系统可以包括聊天服务器和至少一个聊天客户端。 值得注意的是,机器人可以耦合到聊天服务器。 机器人可以被编程为将在聊天服务器中接收到的博客帖子传达给聊天客户端或客户端。 机器人可以进一步编程,以通过联合接口将从聊天客户端或客户端接收到的博客帖子的响应传达给博客。

    BLOCK-BASED BRANCH TARGET ADDRESS CACHE
    30.
    发明申请
    BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
    基于块的分支目标地址高速缓存

    公开(公告)号:US20070266228A1

    公开(公告)日:2007-11-15

    申请号:US11382527

    申请日:2006-05-10

    IPC分类号: G06F15/00

    CPC分类号: G06F9/3806 G06F9/3836

    摘要: A Branch Target Address Cache (BTAC) stores a plurality of entries, each BTAC entry associated with a block of two or more instructions that includes at least one branch instruction having been evaluated taken. The BTAC entry includes an indicator of which instruction within the associated block is a taken branch instruction. The BTAC entry also includes the Branch Target Address (BTA) of the taken branch. The block size may, but does not necessarily, correspond to the number of instructions per instruction cache line.

    摘要翻译: 分支目标地址缓存(BTAC)存储多个条目,每个BTAC条目与包括已经被评估的至少一个分支指令的两个或更多个指令的块相关联。 BTAC条目包括关联块内哪个指令是采取的分支指令的指示符。 BTAC条目还包括采集分支的分行目标地址(BTA)。 块大小可以但不一定对应于每条指令高速缓存线的指令数。