公开(公告)号：US06601146B2

公开(公告)日：2003-07-29

申请号：US09098061

申请日：1998-06-16

Applicant: Marc Alan Auslander ,  David Joel Edelsohn ,  Hubertus Franke ,  Orran Yaakov Krieger ,  Bryan Savoye Rosenburg ,  Robert William Wisniewski

Inventor： Marc Alan Auslander ,  David Joel Edelsohn ,  Hubertus Franke ,  Orran Yaakov Krieger ,  Bryan Savoye Rosenburg ,  Robert William Wisniewski

IPC: G06F1200

CPC classification number: H04L29/06 ,  G06F9/544

Abstract: A method and apparatus for performing efficient interprocess communication (IPC) in a computer system. With this invention, a memory region called the IPC transfer region is shared among all processes of the system to enable more efficient IPC. The unique physical address of the region is mapped into a virtual address from each of the address spaces of the processes of the system. When one of the processes needs to transfer data to another of the processes, the first process stores arguments describing the data in the region using the virtual address in its address space that maps into the unique physical address. When the other or second process needs to receive the data, the second process reads the data from the second region using the virtual address in its memory space that maps into the unique physical address. With this invention, in most cases, control of the IPC transfer region occurs automatically without any kernel intervention.

Abstract translation: 一种用于在计算机系统中执行有效的进程间通信（IPC）的方法和装置。 利用本发明，在系统的所有进程之间共享称为IPC传送区域的存储区域，以实现更高效的IPC。 区域的唯一物理地址被映射到系统进程的每个地址空间的虚拟地址。 当其中一个进程需要将数据传输到另一个进程时，第一个进程使用映射到唯一物理地址的地址空间中的虚拟地址来存储描述该区域中的数据的参数。 当另一个或第二个进程需要接收数据时，第二个进程使用映射到唯一物理地址的存储空间中的虚拟地址从第二个区域读取数据。 利用本发明，在大多数情况下，IPC传送区域的控制自动发生，无需任何内核干预。

公开(公告)号：US06587865B1

公开(公告)日：2003-07-01

申请号：US09157479

申请日：1998-09-21

Applicant: Tracy Jay Kimbrel ,  Marc Alan Auslander ,  David Joel Edelsohn ,  Hubertus Franke ,  Orran Yaakov Krieger ,  Bryan Savoye Rosenburg ,  Robert William Wisniewski

Inventor： Tracy Jay Kimbrel ,  Marc Alan Auslander ,  David Joel Edelsohn ,  Hubertus Franke ,  Orran Yaakov Krieger ,  Bryan Savoye Rosenburg ,  Robert William Wisniewski

IPC: G06F900

CPC classification number: G06F9/4881 ,  G06F9/50

Abstract: In a computer system, a method and apparatus for scheduling activities' access to a resource with minimal involvement of the kernel of the operating system. More specifically, a “next bid” is maintained, and this parameter identifies the highest bid for the resource by any activity not currently accessing the resource. The accessing activity then compares its bid, which can be time varying, with the “next bid” to determine whether it should release the resource to another activity. The “next bid” can be accessed without any system calls to the operating system. This allows the activity to determine whether to relinquish control to the system without the necessity of communication between the two. Likewise, the operating system can access the bid of the accessing activity without explicit communication. This allows the system to determine whether to preempt the accessing activity without the necessity of communication between the two.

Abstract translation: 在计算机系统中，一种方法和装置，用于以最少的操作系统的内核参与调度活动对资源的访问。 更具体地说，维持“下一个出价”，并且该参数通过当前未访问资源的任何活动来识别该资源的最高出价。 然后，访问活动将其可以随时间变化的出价与“下一个出价”进行比较，以确定是否将资源释放到另一个活动。 无需对操作系统进行任何系统调用即可访问“下一个出价”。 这允许活动确定是否放弃对系统的控制，而不需要两者之间的通信。 同样，操作系统可以访问访问活动的出价而不进行明确的通信。 这允许系统确定是否抢占访问活动，而不需要两者之间的通信。

公开(公告)号：US06331873B1

公开(公告)日：2001-12-18

申请号：US09204483

申请日：1998-12-03

Applicant: Barry E. Burke ,  Eugene D. Savoye

Inventor： Barry E. Burke ,  Eugene D. Savoye

IPC: H04N314

CPC classification number: H01L27/14887

Abstract: Provided is a blooming control structure for an imager and a corresponding fabrication method. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate. The blooming barrier region is of a conductivity type and level that is selected based on the blooming barrier width to produce a corresponding electrical potential barrier between the charge collection and blooming drain regions. This blooming control structure, and particularly the blooming barrier regions of the structure, are very precisely defined by the selected acute blooming barrier impurity implantation angle, and optionally in addition by a rotation of the blooming barrier impurity implantation, as well as a non-vertical sidewall profile of the an impurity implantation masking layer.

Abstract translation: 提供了一种用于成像器的开花控制结构和相应的制造方法。 该结构在构成电荷收集区域的半导体衬底中产生。 电荷收集区域被配置为累积在基板中光生的电荷，直到特征的电荷收集能力。 在基板中配置着与电荷收集区域横向隔开的开放的漏极区域。 开放漏极区域包括导电类型和电平的延伸路径，其被选择用于超出电荷收集区域的特征电荷收集能力的电荷。 在基板中配置开放的屏障区域，以与电荷收集和起霜漏极区域相邻并且横向间隔开一个遮光宽度。 该势垒宽度对应于与衬底的急剧起霜阻挡杂质注入角度。 起霜屏障区域是基于开花势垒宽度选择的导电类型和电平，以在电荷收集和起霜漏极区域之间产生相应的电势势垒。 这种起霜控制结构，特别是结构的起霜阻挡区域，通过所选择的急性喷射阻挡杂质注入角度非常精确地限定，并且可选地通过喷霜阻挡杂质注入的旋转以及非垂直 杂质注入掩模层的侧壁轮廓。

公开(公告)号：US5712498A

公开(公告)日：1998-01-27

申请号：US703070

申请日：1996-08-26

Applicant: Robert K. Reich ,  Eugene D. Savoye ,  Bernard B. Kosicki

Inventor： Robert K. Reich ,  Eugene D. Savoye ,  Bernard B. Kosicki

IPC: H01L29/768 ,  H01L31/112 ,  H01L29/80

CPC classification number: H01L29/76833 ,  H01L27/1464 ,  H01L31/1126

Abstract: A charge modulation device having a semiconductor region of a first conductivity type. An epitaxial layer of second conductivity type is provided on a portion of the semiconductor region so as to define an FET channel region. A first epitaxial region of the second conductivity type is provided adjacent to and in contact with the epitaxial layer so as to define an FET drain region, the first epitaxial region being electrically isolated from the semiconductor region. A second epitaxial region of the second conductivity type is provided adjacent to and in contact with the epitaxial layer so as to define an FET source region, the second epitaxial region being electrically isolated from the semiconductor region. A third epitaxial region of the first conductivity type or a metal oxide semiconductor is provided to the channel region between the source and drain regions.

Abstract translation: 一种具有第一导电类型的半导体区域的电荷调制装置。 在半导体区域的一部分上设置第二导电类型的外延层，以限定FET沟道区。 第二导电类型的第一外延区域设置成与外延层相邻并与外延层接触，以便限定FET漏区，该第一外延区域与半导体区域电绝缘。 第二导电类型的第二外延区域被设置为与外延层相邻并与外延层接触，以限定FET源极区域，第二外延区域与半导体区域电绝缘。 第一导电类型的第三外延区域或金属氧化物半导体被提供到源极和漏极区域之间的沟道区域。

公开(公告)号：US1125734A

公开(公告)日：1915-01-19

申请号：US1913761039

申请日：1913-04-14

Applicant: SAVOYE RENE ,  ZACCONI HENRI

Inventor： SAVOYE RENE ,  ZACCONI HENRI

IPC: B42F17/00

CPC classification number: B42F17/00

公开(公告)号：US1125733A

公开(公告)日：1915-01-19

申请号：US1912735842

申请日：1912-12-09

Applicant: SAVOYE RENE ,  DRYVERS URBAIN

Inventor： SAVOYE RENE ,  DRYVERS URBAIN

CPC classification number: G10F1/02

公开(公告)号：US845582A

公开(公告)日：1907-02-26

申请号：US1905283249

申请日：1905-10-18

Applicant: SAVOYE EMILE

Inventor： SAVOYE EMILE

CPC classification number: A41C3/00

公开(公告)号：US740930A

公开(公告)日：1903-10-06

申请号：US1903161702

申请日：1903-06-16

Applicant: SAVOYE EMILE

Inventor： SAVOYE EMILE

CPC classification number: A41C1/00

公开(公告)号：US11649114B2

公开(公告)日：2023-05-16

申请号：US16881960

申请日：2020-05-22

Applicant: Savoye

Inventor： Stephane Pietrowicz

IPC: G06F7/00 ,  B65G1/137 ,  B65G47/88 ,  G05B19/042 ,  G06Q10/0631 ,  G06Q50/28

CPC classification number: B65G1/1376 ,  B65G47/8807 ,  G05B19/042 ,  G06Q10/06312 ,  G06Q10/06315 ,  G06Q10/06316 ,  G06Q50/28 ,  B65G2201/025 ,  B65G2203/0233 ,  G05B2219/2621

Abstract: Processing a list of customer orders with a control system and a preparing station, which includes a picking position, an insertion position and local recirculation. The control system: selects a reference in the greatest number of order lines of the list; determines a set E of all the NE orders each containing an order line containing the selected reference; creates a group G of N orders that are the NE orders, if NE≤Nmax with Nmax being a predetermined threshold, or the Nmax first orders of the NE orders sorted according to decreasing order of priority, if NE>Nmax; builds a list LC of the K order lines in the N orders of the group G; and controls the system to bring source loads to the picking position and ship loads to the insertion position and to make the shipping loads recirculate to the insertion position, according to the list LC.

公开(公告)号：US11155410B2

公开(公告)日：2021-10-26

申请号：US16196694

申请日：2018-11-20

Applicant: SAVOYE

Inventor： Dominique Testa ,  Anne Boudalier

IPC: B65G1/10 ,  B65G1/137 ,  G07C9/00 ,  B65G1/14 ,  G07F11/16 ,  G07F17/12

Abstract: An automatic locker device is configured for handling loads with operations of loading and retrieval. The device includes at least one storage zone for storing loads, at least one retrieval point and a handling mechanism, which is configured to move the loads from the at least one storage zone to the at least one retrieval point, for the retrieval operations. The automatic locker device also includes at least one buffer zone, distinct from the at least one storage zone. The handling mechanism is configured to move the loads from the at least one buffer zone to the at least one storage zone, for the loading operations.