公开(公告)号：US5760431A

公开(公告)日：1998-06-02

申请号：US708610

申请日：1996-09-05

Applicant: Eugene D. Savoye ,  Barry E. Burke ,  John Tonry

Inventor： Eugene D. Savoye ,  Barry E. Burke ,  John Tonry

IPC: H01L27/148 ,  H01L29/10 ,  H01L29/768

CPC classification number: H01L29/76858 ,  H01L27/1464 ,  H01L27/14831 ,  H01L29/1062

Abstract: A multidirectional charge transfer device configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates, each of which is arranged in a first portion of each charge storage region, a plurality of second gates, each of which is arranged in a second portion of each charge storage region, a plurality of third gates, each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates, each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.

Abstract translation: 一种配置在电荷存储介质中的多向电荷转移装置。 该装置包括电荷存储区域的阵列。 每个所述电荷存储区域包括多个第一栅极，每个第一栅极布置在每个电荷存储区域的第一部分中，多个第二栅极，每个第二栅极布置在每个电荷存储区域的第二部分中， 多个第三栅极，每个第三栅极布置在每个电荷存储区域的第三部分中，以及多个第四栅极，每个栅极布置在每个电荷存储区域的第四部分中。 多个栅极和电荷存储区被配置为限定相对于彼此非共线的至少三个双向电荷传输路径。 多个栅极被顺序地偏置以沿着所述双向电荷转移路径之一建立电荷转移，并形成阻挡电位以在剩余电荷转移路径中进行电荷转移。

公开(公告)号：US5270558A

公开(公告)日：1993-12-14

申请号：US24805

申请日：1993-03-01

Applicant: Robert K. Reich ,  Bernard Kosicki ,  Eugene D. Savoye

Inventor： Robert K. Reich ,  Bernard Kosicki ,  Eugene D. Savoye

IPC: H01L27/148 ,  H01L29/10 ,  H01L29/796

CPC classification number: H01L29/1091 ,  H01L27/14831

Abstract: A charge-coupled device having an array of pixel elements formed in a substrate, which device is operable in a first state to expand the depletion well regions of each pixel element into the substrate for storing incoming photoelectrons therein and in a second state to contract the expanded depletion well regions to prevent storage of photoelectrons in the contracted depletion well regions.

Abstract translation: 一种具有形成在衬底中的像素元件阵列的电荷耦合器件，该器件可在第一状态下操作，以将每个像素元件的耗尽阱区域扩展到衬底中，用于存储入射光电子，并且在第二状态下收缩 扩大的耗尽井区域以防止光电子在收缩的耗尽井区域中储存。

公开(公告)号：US4661854A

公开(公告)日：1987-04-28

申请号：US813423

申请日：1985-12-26

Applicant: Eugene D. Savoye

Inventor： Eugene D. Savoye

IPC: H01L27/148 ,  H01L27/14 ,  H04N5/359 ,  H04N5/3728 ,  H04N3/14

CPC classification number: H04N5/3595

Abstract: Significant reductions in transfer smear for charge sweep device imagers is made possible by performing the charge sweep operation during only the line retrace period of the operating cycle of the imager. Complete elimination of transfer smear is then possible by using an optical means for blocking the imager from incident illumination during said line retrace periods.

Abstract translation: 通过仅在成像器的操作周期的线回扫期间执行充电扫描操作，可以大大减少电荷扫描装置成像器的转印拖尾。 通过使用光学装置，可以完全消除转印涂片，从而在所述线回扫期间阻挡成像仪进入入射照明。

公开(公告)号：US4658497A

公开(公告)日：1987-04-21

申请号：US740719

申请日：1985-06-03

Applicant: Eugene D. Savoye ,  Walter F. Kosonocky ,  Lloyd F. Wallace

Inventor： Eugene D. Savoye ,  Walter F. Kosonocky ,  Lloyd F. Wallace

IPC: H01L27/148 ,  H01L31/18 ,  H01L21/26

CPC classification number: H01L27/14887 ,  H01L31/18 ,  Y10S148/083

Abstract: An imaging array of the charge transfer type having improved sensitivity is disclosed. The array includes a plurality of substantially parallel charge transfer channels with channel stops therebetween which extend a distance into a semiconductor body. At least some of the channel stops have blooming drains therein for the removal of excess photogenerated charge. The improvement comprises potential barrier means which constrain electrical charge generated by absorption of light in the body to flow into the channels while preventing the loss of such charge by direct flow to the blooming drains. Potential barrier means include buried barrier regions extending a further distance into the body from those channel stops having blooming drain regions therein.The invention also includes an improved method of forming this array wherein the improvement comprises forming buried barrier regions containing a greater concentration of conductivity modifiers than the channel stops after the blooming drains are formed.

Abstract translation: 公开了具有改进的灵敏度的电荷转移类型的成像阵列。 该阵列包括多个基本上平行的电荷传输通道，其间具有通道阻挡件，其延伸到半导体本体中的距离。 至少一些通道挡板在其中具有开口的排水口以去除过量的光生电荷。 该改进包括势垒装置，其限制通过吸收身体中的光而产生的电荷流入通道，​​同时通过直接流动到开花的排水口来防止这种电荷的损失。 电势屏障装置包括从其中具有开放漏极区的那些通道阻挡区向主体延伸更远距离的掩埋阻挡区域。 本发明还包括形成该阵列的改进方法，其中改进包括形成掩埋阻挡区域，该掩埋阻挡区域包含比形成开花排水道之后的通道停止的更大浓度的导电性改进剂。

公开(公告)号：US4580169A

公开(公告)日：1986-04-01

申请号：US681437

申请日：1984-12-12

Applicant: Eugene D. Savoye

Inventor： Eugene D. Savoye

IPC: H01L27/148 ,  H04N5/353 ,  H04N5/372 ,  H04N3/15

CPC classification number: H04N3/1543 ,  H01L27/1464 ,  H01L27/14831

Abstract: A CCD imager of field transfer type having an image register statically clocked during image integration in a number of phases greater than it is dynamically clocked with during field transfer to a field storage register, when the image register and the field storage register are clocked in synchronous phase with each other.

Abstract translation: 当图像寄存器和场存储寄存器以同步方式计时时，具有在图像积分期间以大于其的多个相位静态计时的图像寄存器的CCD成像器在场传输到场存储寄存器期间被动态计时 相互相邻。

公开(公告)号：US06331873B1

公开(公告)日：2001-12-18

申请号：US09204483

申请日：1998-12-03

Applicant: Barry E. Burke ,  Eugene D. Savoye

Inventor： Barry E. Burke ,  Eugene D. Savoye

IPC: H04N314

CPC classification number: H01L27/14887

Abstract: Provided is a blooming control structure for an imager and a corresponding fabrication method. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate. The blooming barrier region is of a conductivity type and level that is selected based on the blooming barrier width to produce a corresponding electrical potential barrier between the charge collection and blooming drain regions. This blooming control structure, and particularly the blooming barrier regions of the structure, are very precisely defined by the selected acute blooming barrier impurity implantation angle, and optionally in addition by a rotation of the blooming barrier impurity implantation, as well as a non-vertical sidewall profile of the an impurity implantation masking layer.

Abstract translation: 提供了一种用于成像器的开花控制结构和相应的制造方法。 该结构在构成电荷收集区域的半导体衬底中产生。 电荷收集区域被配置为累积在基板中光生的电荷，直到特征的电荷收集能力。 在基板中配置着与电荷收集区域横向隔开的开放的漏极区域。 开放漏极区域包括导电类型和电平的延伸路径，其被选择用于超出电荷收集区域的特征电荷收集能力的电荷。 在基板中配置开放的屏障区域，以与电荷收集和起霜漏极区域相邻并且横向间隔开一个遮光宽度。 该势垒宽度对应于与衬底的急剧起霜阻挡杂质注入角度。 起霜屏障区域是基于开花势垒宽度选择的导电类型和电平，以在电荷收集和起霜漏极区域之间产生相应的电势势垒。 这种起霜控制结构，特别是结构的起霜阻挡区域，通过所选择的急性喷射阻挡杂质注入角度非常精确地限定，并且可选地通过喷霜阻挡杂质注入的旋转以及非垂直 杂质注入掩模层的侧壁轮廓。

公开(公告)号：US5712498A

公开(公告)日：1998-01-27

申请号：US703070

申请日：1996-08-26

Applicant: Robert K. Reich ,  Eugene D. Savoye ,  Bernard B. Kosicki

Inventor： Robert K. Reich ,  Eugene D. Savoye ,  Bernard B. Kosicki

IPC: H01L29/768 ,  H01L31/112 ,  H01L29/80

CPC classification number: H01L29/76833 ,  H01L27/1464 ,  H01L31/1126

Abstract: A charge modulation device having a semiconductor region of a first conductivity type. An epitaxial layer of second conductivity type is provided on a portion of the semiconductor region so as to define an FET channel region. A first epitaxial region of the second conductivity type is provided adjacent to and in contact with the epitaxial layer so as to define an FET drain region, the first epitaxial region being electrically isolated from the semiconductor region. A second epitaxial region of the second conductivity type is provided adjacent to and in contact with the epitaxial layer so as to define an FET source region, the second epitaxial region being electrically isolated from the semiconductor region. A third epitaxial region of the first conductivity type or a metal oxide semiconductor is provided to the channel region between the source and drain regions.

Abstract translation: 一种具有第一导电类型的半导体区域的电荷调制装置。 在半导体区域的一部分上设置第二导电类型的外延层，以限定FET沟道区。 第二导电类型的第一外延区域设置成与外延层相邻并与外延层接触，以便限定FET漏区，该第一外延区域与半导体区域电绝缘。 第二导电类型的第二外延区域被设置为与外延层相邻并与外延层接触，以限定FET源极区域，第二外延区域与半导体区域电绝缘。 第一导电类型的第三外延区域或金属氧化物半导体被提供到源极和漏极区域之间的沟道区域。

公开(公告)号：US07074639B2

公开(公告)日：2006-07-11

申请号：US10023387

申请日：2001-12-17

Applicant: Barry E. Burke ,  Eugene D. Savoye

Inventor： Barry E. Burke ,  Eugene D. Savoye

IPC: H01L21/00

CPC classification number: H01L27/14887

Abstract: Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate. The blooming barrier region is of a conductivity type and level that is selected based on the blooming barrier width to produce a corresponding electrical potential barrier between the charge collection and blooming drain regions. The blooming barrier regions of the structure are very precisely defined by the selected acute blooming barrier impurity implantation angle, and optionally in addition by a rotation of the blooming barrier impurity implantation, as well as a non-vertical sidewall profile of the an impurity implantation masking layer.

公开(公告)号：US4716447A

公开(公告)日：1987-12-29

申请号：US904805

申请日：1986-09-08

Applicant: Eugene D. Savoye

Inventor： Eugene D. Savoye

IPC: H01L27/148 ,  H04N5/359 ,  H04N5/372 ,  H01L29/78 ,  H01L27/12 ,  H01L27/14 ,  H01L31/00

CPC classification number: H04N3/1556 ,  H01L27/1464 ,  H01L27/14887

Abstract: Charge integration is selectively interrupted in a semiconductor imager with thinned substrate, by modulating the electric field normal to its back-illuminated surface. This suppresses smear generated during field transfer in certain types of imager when exposed to high-energy images, for example. The thinned substrate is cemented with an electrically insulating epoxy to a glass backing plate bearing a transparent electrode, the potential on which is varied to modulate the drift field.

Abstract translation: 通过调制与其背面照射的表面垂直的电场，在具有薄化衬底的半导体成像器中选择性地中断电荷积分。 这样，例如，当暴露于高能量图像时，这抑制了在某些类型的成像器中的场传输期间产生的拖尾。 将薄的衬底与电绝缘环氧树脂粘合到具有透明电极的玻璃背板上，其上的电位被改变以调节漂移场。

公开(公告)号：US4481538A

公开(公告)日：1984-11-06

申请号：US428589

申请日：1982-09-30

Applicant: Donald F. Battson ,  Eugene D. Savoye

Inventor： Donald F. Battson ,  Eugene D. Savoye

IPC: H04N5/357 ,  H04N5/3725 ,  H04N5/376 ,  H04N3/15

CPC classification number: H04N3/1543

Abstract: Field-rate flicker is suppressed in a CCD imager having a three-phase operated image register provided interlacing by integrating odd-numbered fields with only the first clock phase high and even-numbered fields with only the second and third clock phases high. The flicker is suppressed by making the gate electrodes in the A register receiving the second and third clock phases of equal lengths, half that of the gate electrodes receiving the first clock phase.

Abstract translation: 在具有三相运算图像寄存器的CCD成像器中，通过将奇数场与只有第二和第三时钟相位的第一时钟相位高和偶数场积分而使奇数编号的场进行积分，在CCD成像器中抑制了场速闪烁。 通过使A寄存器中的栅电极接收相等长度的第二和第三时钟相位来抑制闪烁，其中一半是接收第一时钟相位的栅电极。