DEBUGGING SUPPORT UNIT FOR MICROPROCESSOR
    21.
    发明申请

    公开(公告)号:US20170322867A1

    公开(公告)日:2017-11-09

    申请号:US15203659

    申请日:2016-07-06

    Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.

    DRIVING CIRCUIT FOR POWER SWITCH
    23.
    发明申请

    公开(公告)号:US20170237421A1

    公开(公告)日:2017-08-17

    申请号:US15052170

    申请日:2016-02-24

    Inventor: Zhenghao Cui

    CPC classification number: H03K17/04106 H03K17/165

    Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.

    SUBJECT MONITOR
    24.
    发明申请
    SUBJECT MONITOR 审中-公开
    主体监视器

    公开(公告)号:US20160146848A1

    公开(公告)日:2016-05-26

    申请号:US14986448

    申请日:2015-12-31

    Abstract: An embodiment includes an apparatus with a housing wearable by a subject and a first sensor operable to detect a position of the subject. An embodiment of the apparatus includes a second sensor operable to detect a body state of the subject, where the first body state may be a vital sign such as heart rate, blood pressure, body temperature or respiratory rate. The apparatus may also include a wireless module, and be operable to transmit body state data and position data to a remote device. The apparatus may include a gyroscope or an accelerometer, and may be operable to detect rotational change in the subject's position about an axis, linear acceleration of the subject along an axis, a change in position of the subject, or a rate of change in position of the subject.

    Abstract translation: 一个实施例包括具有由被摄体佩戴的外壳的装置和可操作以检测被摄体位置的第一传感器。 该装置的实施例包括可操作以检测被检体的身体状态的第二传感器,其中第一身体状态可以是诸如心率,血压,体温或呼吸频率的生命体征。 该装置还可以包括无线模块,并且可操作以将身体状态数据和位置数据传送到远程设备。 该装置可以包括陀螺仪或加速度计,并且可以操作以检测被摄体围绕轴的位置的旋转变化,对象沿着轴的线性加速度,对象的位置变化或位置变化率 的主题。

    PEAK-TO-AVERAGE POWER RATIO (PAR) REDUCTION BASED ON ACTIVE-SET TONE RESERVATION
    25.
    发明申请
    PEAK-TO-AVERAGE POWER RATIO (PAR) REDUCTION BASED ON ACTIVE-SET TONE RESERVATION 有权
    基于主动设置音调预留的峰值平均功率比(PAR)减小

    公开(公告)号:US20130343482A1

    公开(公告)日:2013-12-26

    申请号:US13974992

    申请日:2013-08-23

    Inventor: Sen JIANG

    CPC classification number: H04L27/2618 H04L27/0006 H04L27/2614

    Abstract: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.

    Abstract translation: 在一个实施例中,发射机包括第一和第二处理块,其可以各自包括硬件,软件或硬件和软件的组合。 第一处理块可操作以产生第一峰值减小向量。 第二处理块可操作以接收第一数据向量,所述数据向量包括多个样本,所述第一数据向量具有具有第一索引和第一幅度的第一峰值,具有第二索引和第二幅度的第二峰值 小于第一幅度和第一峰均功率比,并且通过以下方式生成具有低于第一峰均功率比的第二峰均功率比的第二数据矢量 使用第一降频矢量。

    Permanent magnet synchronous motor (PMSM) and method for starting the PMSM

    公开(公告)号:US11942882B2

    公开(公告)日:2024-03-26

    申请号:US17828413

    申请日:2022-05-31

    Inventor: Na Zhang

    CPC classification number: H02P21/34 H02P21/10 H02P2207/055

    Abstract: A method of starting a permanent magnet synchronous motor (PMSM) with field oriented control (FOC) includes: opening a first control loop of the PMSM; setting a first direction for a first current component of the PMSM; aligning a rotor of the PMSM to the first direction; after aligning the rotor, setting a second direction for the first current component, where the second direction is rotated from the first direction by 90 degrees; after setting the second direction, starting the rotor while the first control loop of the PMSM remains open; after starting the rotor, increasing a rotation speed of the rotor by operating the first control loop in a first closed-loop mode; and after increasing the rotation speed of the rotor, controlling the rotation speed of the rotor by operating the first control loop in a second closed-loop mode different from the first closed-loop mode.

    Circular buffer accessing device, system and method

    公开(公告)号:US11630671B1

    公开(公告)日:2023-04-18

    申请号:US17581601

    申请日:2022-01-21

    Abstract: A device includes a circular buffer, which, in operation, is organized into a plurality of subsets of buffers, and control circuitry coupled to the circular buffer. The control circuitry, in operation, receives a memory load command to load a set of data into the circular buffer. The memory load command has an offset parameter indicating a data offset and a subset parameter indicating a subset of the plurality of subsets into which the circular buffer is organized. The control circuitry responds to the command by identifying a set of buffer addresses of the circular buffer based on a value of the offset parameter and a value of the subset parameter, and loading the set of data into the circular buffer using the identified set of buffer addresses.

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