公开(公告)号：US20090309633A1

公开(公告)日：2009-12-17

申请号：US12140410

申请日：2008-06-17

申请人： Jeff Kotowski ,  Shane Hollmer

发明人： Jeff Kotowski ,  Shane Hollmer

IPC分类号： H03K3/00 ,  H03L7/06

CPC分类号： H03K17/165

摘要： A ramp-up circuit for switched capacitor circuits with negative feedback to control the slew rate of in-rush current. Other embodiments are described and claimed.

摘要翻译： 用于负反馈的开关电容电路的斜坡上升电路，用于控制浪涌电流的转换速率。 描述和要求保护其他实施例。

公开(公告)号：US07155357B2

公开(公告)日：2006-12-26

申请号：US10339218

申请日：2003-01-09

申请人： Shane Hollmer

发明人： Shane Hollmer

IPC分类号： G06F19/00 ,  G06F9/00

CPC分类号： G06F11/2247 ,  G01R31/31719 ,  G11C7/20 ,  G11C29/12 ,  G11C2029/0407 ,  G11C2029/4402

摘要： An unused state detection circuit is disclosed that detects an unused state in a semiconductor circuit. A semiconductor circuit is “unused” when the unused state detection circuit has not been permanently cleared. When a semiconductor circuit is first powered up, the unused state detection circuit will detect that the semiconductor circuit has not previously been “used” and can automatically activate a boot up procedure or a testing procedure (or both). After the semiconductor circuit is used, the unused state detection circuit provides an indication that the semiconductor circuit is no longer unused. The unused state detection circuit uses the state of a dedicated non-volatile memory array or a dedicated region of the general non-volatile memory portion of the semiconductor circuit to detect whether the semiconductor circuit has been previously unused.

摘要翻译： 公开了一种未使用的状态检测电路，其检测半导体电路中的未使用状态。 当未使用状态检测电路未被永久清除时，半导体电路为“未使用”。 当半导体电路第一次通电时，未使用的状态检测电路将检测到半导体电路以前没有被“使用”，并且可以自动激活引导过程或测试程序（或两者）。 在使用半导体电路之后，未使用的状态检测电路提供半导体电路不再未使用的指示。 未使用状态检测电路使用半导体电路的一般非易失性存储器部分的专用非易失性存储器阵列或专用区域的状态来检测半导体电路是否以前未被使用。

公开(公告)号：US5801579A

公开(公告)日：1998-09-01

申请号：US808237

申请日：1997-02-28

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Shoichi Kawamura ,  Michael Chung ,  Vincent Leung ,  Masaru Yano

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Shoichi Kawamura ,  Michael Chung ,  Vincent Leung ,  Masaru Yano

IPC分类号： G11C8/08 ,  G11C16/12 ,  G05F1/10

CPC分类号： G11C16/12 ,  G11C8/08

摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

摘要翻译： 两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。 两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。 在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。 这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。 在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。 通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。 在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。