公开(公告)号：US5608741A

公开(公告)日：1997-03-04

申请号：US156427

申请日：1993-11-23

Applicant: Sudarshan Kumar ,  Shyue L. Kuo ,  Chung Y. Yip

Inventor： Sudarshan Kumar ,  Shyue L. Kuo ,  Chung Y. Yip

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 2.sup.2n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only ##EQU1## 4-bit XOR cells. For 2.sup.2n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using ##EQU2## 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.

Abstract translation: 本发明公开了一种使用使用补码传输晶体管逻辑实现的4位XOR单元的快速奇偶校验位发生器。 对于22n个输入，其中n是任意正整数，奇偶校验位仅使用 4位XOR单元在n个阶段中生成。 对于22n + 1输入，其中n是任意的正整数，使用放置在最后一行中的n行和一个2位XOR单元中的 4位XOR单元产生奇偶校验位。 通过在XOR单元内使用NMOS晶体管逻辑来进一步增强XOR单元的工作速度。

公开(公告)号：US5581497A

公开(公告)日：1996-12-03

申请号：US325777

申请日：1994-10-17

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/506

CPC classification number: G06F7/506

Abstract: An adder is described. The adder generates a block generate signal after one domino gate delay. The adder can also generate a carry out signal, generate a first plurality of sum signals in response to the carry out signal, generate a block generate signal, generate a group generate signal, and generate a second plurality of sum signals in response to the carry out signal, block generate signal and group generate signal.

Abstract translation: 描述加法器。 加法器在一个多米诺门延迟后产生一个块生成信号。 加法器还可以生成进位信号，响应于进位信号产生第一多个和信号，产生块产生信号，产生组生成信号，并响应于进位产生第二多个和信号 输出信号，块生成信号和组生成信号。

公开(公告)号：US20220012304A1

公开(公告)日：2022-01-13

申请号：US17369801

申请日：2021-07-07

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G06F17/16 ,  G06F5/01 ,  G06F7/544

Abstract: A system and method of multiplying a first matrix and a second matrix is provided, the method comprising compressing the second matrix into a third matrix to process primarily non-zero values. For each row in the first matrix, a row may be loaded into a row lookup unit. For each entry in the third matrix, a row address may be extracted, a row value may be obtained from a corresponding loaded row of the first matrix based on the extracted row address, the row value from the loaded row may be multiplied with the matrix value from the third matrix for each column, and the multiplied value may be added to an accumulator corresponding to the each column. Lastly, a multiplied matrix may be output for the loaded row.

公开(公告)号：US06833735B2

公开(公告)日：2004-12-21

申请号：US10335141

申请日：2002-12-31

Applicant: Sudarshan Kumar ,  Jiann-Cherng Lan ,  Snehal Jariwala ,  Wenjie Jiang

Inventor： Sudarshan Kumar ,  Jiann-Cherng Lan ,  Snehal Jariwala ,  Wenjie Jiang

IPC: H03K19096

CPC classification number: H03K19/0963

Abstract: A complementary metal oxide semiconductor (CMOS) low-power, high speed logic circuit consisting of a cascaded chain of stages. The first stage is a pulsed domino logic circuit having one or more logic signal inputs for receiving data signals, and a timing input for receiving a clocking pulse that conditions the input pulse domino stage for evaluation during a brief window of time. The output of the pulsed domino circuit is connected to a chain of series-connected skewed static logic gates, each having the channel sizes of its pull-up and pull-down transistors ratioed to a produce, from gate-to-gate in the static logic chain, alternating fast high-to-low and low-to-high transitions for the information carrying leading edge of said input data signals. The use of a pulsed domino first stage driving a chain of skewed logic static gates reduces power consumption but retains the speed of conventional domino logic circuits.

Abstract translation: 一种互补的金属氧化物半导体（CMOS）低功耗高速逻辑电路，由级联的级联链组成。 第一级是具有用于接收数据信号的一个或多个逻辑信号输入的脉冲多米诺逻辑电路，以及用于接收时钟脉冲的定时输入，用于在简短的时间窗口期间控制输入脉冲多米诺骨架级以进行评估。 脉冲多米诺骨电路的输出连接到串联连接的偏斜静态逻辑门，每条链的上拉和下拉晶体管的沟道尺寸与产品的栅极到栅极的静态 逻辑链，用于传送所述输入数据信号前沿的信息的交替快速高到低和从低到高的转变。 使用脉冲多米诺骨牌第一阶段驱动偏斜逻辑静态门链降低了功耗，但保留了常规多米诺逻辑电路的速度。

公开(公告)号：US06820106B1

公开(公告)日：2004-11-16

申请号：US09604620

申请日：2000-06-27

Applicant: Narsing K. Vijayrao ,  Chi Keung Lee ,  Sudarshan Kumar

Inventor： Narsing K. Vijayrao ,  Chi Keung Lee ,  Sudarshan Kumar

IPC: G06F738

CPC classification number: G06F7/5443 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49957 ,  G06F7/74

Abstract: A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position. The apparatus comprises a multiplier with a propagate, kill, generate generator (PKG generator) coupled to it. An adder, a plus-oner, a plus-two-er and a leading zero anticipator (LZA) are each coupled to the PKG generator in parallel. A rounding control unit is coupled to the LZA and coupled to a multiplexor that outputs a result from one of the adder, the plus-oner, and the plus-two-er responsive to the rounding control unit. A normalization shifter is coupled to the multiplexor and the LZA.

Abstract translation: 一种提高浮点乘法器累加器（FMAC）性能的方法和装置。 该方法包括接收三个浮点数并计算第一个浮点数和第二个浮点数的乘积，并加上第三个浮点数以产生一个和值和一个进位值。 然后根据和值和进位值计算传播值，杀死值和生成值。 同时将总和值加到进位值以创建第一个结果，将和值添加到进位值并递增1以创建第二个结果，将总和值添加到进位值并递增2以创建 确定第三结果和小数点位置。 然后根据舍入模式和小数点位置选择第一个结果之一，第二个结果和第三个结果。 所选结果根据小数点位置进行归一化。 该装置包括具有耦合到其的传播，杀死，生成发生器（PKG发生器）的乘法器。 加法器，加法器，加二和前导零预测器（LZA）均并联耦合到PKG发生器。 四舍五入控制单元耦合到LZA，并且耦合到多路复用器，该多路复用器响应于舍入控制单元输出加法器，加上器和加二乘法器中的一个的结果。 归一化移位器耦合到多路复用器和LZA。

公开(公告)号：US06629194B2

公开(公告)日：2003-09-30

申请号：US09872965

申请日：2001-05-31

Applicant: Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

Inventor： Sudarshan Kumar ,  Gaurav G. Mehta ,  Sadhana Madhyastha ,  Jiann-Cherng Lan

IPC: G06F1200

CPC classification number: G06F9/30141 ,  G06F9/3012 ,  G11C7/12 ,  G11C2207/007 ,  G11C2207/2281

Abstract: A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.

公开(公告)号：US06205463B1

公开(公告)日：2001-03-20

申请号：US08850989

申请日：1997-05-05

Applicant: Rajesh Manglore ,  Sudarshan Kumar

Inventor： Rajesh Manglore ,  Sudarshan Kumar

IPC: G06F750

CPC classification number: G06F7/508

Abstract: In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.

Abstract translation: 在一个实施例中，加法器被分割成多个操作块; 即第一块，第二块和第三块。 第一部分中的第一块产生和位和区段进位信号。 第二部分中的第二块产生第二多个和位和第一块进位信号。 第二部分中的第三块接收片段进位信号和第一块进位信号。 第三块包括进位处理器，其接收段进位信号并输出​​对应于第三块的第二块进位信号。

公开(公告)号：US6023767A

公开(公告)日：2000-02-08

申请号：US841839

申请日：1997-05-05

Applicant: Sudarshan Kumar ,  James J. C. Lan ,  Rajesh Manglore

Inventor： Sudarshan Kumar ,  James J. C. Lan ,  Rajesh Manglore

IPC: G06F1/10 ,  G06F1/04

CPC classification number: G06F1/10

Abstract: A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.

Abstract translation: 一种用于验证电子设备的第一电路和第二电路之间的适当通信的方法。 首先确定第一电路和第二电路定时的哪个全局时钟。 然后，如果确定第一和第二存储电路由不同的全局时钟定时，则时钟信号在第一和第二存储电路之间移动等于或大于设备的全局时钟偏差预算的量。 最后，根据设备的本地时钟偏差预算验证第二电路的正确操作。

公开(公告)号：US5661675A

公开(公告)日：1997-08-26

申请号：US414908

申请日：1995-03-31

Applicant: Kai J. Chin ,  Sudarshan Kumar

Inventor： Kai J. Chin ,  Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/508 ,  H03K19/096 ,  H03K17/80

CPC classification number: G06F7/508 ,  H03K19/0963 ,  G06F2207/3872

Abstract: A logic circuit is described. The logic circuit generates a first signal state in response to a first set of input signals, generates a second signal state in response to a second set of input signals, activates a bypass switch in response to the first signal state, and bypasses a domino logic unit in response to the first signal state.

Abstract translation: 描述逻辑电路。 逻辑电路响应于第一组输入信号产生第一信号状态，响应于第二组输入信号产生第二信号状态，响应于第一信号状态激活旁路开关，并绕过多米诺逻辑 响应于第一信号状态的单元。

公开(公告)号：US5136539A

公开(公告)日：1992-08-04

申请号：US285202

申请日：1988-12-16

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/507 ,  G06F7/508

CPC classification number: G06F7/506 ,  G06F7/508

Abstract: An metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals. For a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.

Abstract translation: 由多个四位片块制造的金属氧化物半导体（MOS）分区进位前瞻加法器。 每个块提供四个和信号并提供块进位信号。 块被组织成最佳尺寸的组，每组中具有逻辑以产生组传播信号。 每个块具有块载入线，其中单个晶体管连接在块的输入和输出端子之间。 块使用中间携带电路来计算总和代替全加器。 此外，还有一个主输送线，晶体管由组传播信号控制。 对于32位加法器，进位链中的最大通过门延迟是三通门。