公开(公告)号：US06833735B2

公开(公告)日：2004-12-21

申请号：US10335141

申请日：2002-12-31

申请人： Sudarshan Kumar ,  Jiann-Cherng Lan ,  Snehal Jariwala ,  Wenjie Jiang

发明人： Sudarshan Kumar ,  Jiann-Cherng Lan ,  Snehal Jariwala ,  Wenjie Jiang

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A complementary metal oxide semiconductor (CMOS) low-power, high speed logic circuit consisting of a cascaded chain of stages. The first stage is a pulsed domino logic circuit having one or more logic signal inputs for receiving data signals, and a timing input for receiving a clocking pulse that conditions the input pulse domino stage for evaluation during a brief window of time. The output of the pulsed domino circuit is connected to a chain of series-connected skewed static logic gates, each having the channel sizes of its pull-up and pull-down transistors ratioed to a produce, from gate-to-gate in the static logic chain, alternating fast high-to-low and low-to-high transitions for the information carrying leading edge of said input data signals. The use of a pulsed domino first stage driving a chain of skewed logic static gates reduces power consumption but retains the speed of conventional domino logic circuits.

摘要翻译： 一种互补的金属氧化物半导体（CMOS）低功耗高速逻辑电路，由级联的级联链组成。 第一级是具有用于接收数据信号的一个或多个逻辑信号输入的脉冲多米诺逻辑电路，以及用于接收时钟脉冲的定时输入，用于在简短的时间窗口期间控制输入脉冲多米诺骨架级以进行评估。 脉冲多米诺骨电路的输出连接到串联连接的偏斜静态逻辑门，每条链的上拉和下拉晶体管的沟道尺寸与产品的栅极到栅极的静态 逻辑链，用于传送所述输入数据信号前沿的信息的交替快速高到低和从低到高的转变。 使用脉冲多米诺骨牌第一阶段驱动偏斜逻辑静态门链降低了功耗，但保留了常规多米诺逻辑电路的速度。

公开(公告)号：US06631093B2

公开(公告)日：2003-10-07

申请号：US09895361

申请日：2001-06-29

申请人： Sudarshan Kumar ,  Jiann-Cherng Lan ,  Wenjie Jiang ,  Gaurav Mehta ,  Sadhana Madhyastha

发明人： Sudarshan Kumar ,  Jiann-Cherng Lan ,  Wenjie Jiang ,  Gaurav Mehta ,  Sadhana Madhyastha

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.

摘要翻译： 低功耗存储器位线预充电方案。 存储器位线耦合到第一读取预充电器件。 第二写入预充电装置也耦合到存储器位线，并且仅在响应于存储器写入操作时被使能。 第一读取和第二写入预充电装置的尺寸使其组合的驱动强度足以在写操作之后的预充电期间对第一存储器位线进行预充电。

公开(公告)号：US6111435A

公开(公告)日：2000-08-29

申请号：US343961

申请日：1999-06-30

申请人： Jiann-Cherng James Lan ,  Mahadevamurty Nemani ,  Narsing K. Vijayrao ,  Wenjie Jiang ,  Sudarshan Kumar

发明人： Jiann-Cherng James Lan ,  Mahadevamurty Nemani ,  Narsing K. Vijayrao ,  Wenjie Jiang ,  Sudarshan Kumar

IPC分类号： H03K17/693 ,  H03K19/173 ,  H03K19/20

CPC分类号： H03K17/693 ,  H03K19/1731

摘要： A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.

摘要翻译： 电路包括第一和第二上拉晶体管，其分别具有分别耦合到单独的电压钳位的第一和第二漏极。 两个上拉晶体管中的每一个的栅极耦合到时钟信号线。 电路还包括共享下拉晶体管，其栅极耦合到时钟信号线。 共享下拉晶体管的漏极经由与共用下拉晶体管串联的至少一个下拉晶体管耦合到第一漏极。 共享下拉晶体管的漏极还通过与共享下拉晶体管串联的至少一个下拉晶体管耦合到第二漏极。 该电路可用于多路复用应用。

公开(公告)号：US06292029B1

公开(公告)日：2001-09-18

申请号：US09471650

申请日：1999-12-23

申请人： Sudarshan Kumar ,  Wenjie Jiang

发明人： Sudarshan Kumar ,  Wenjie Jiang

IPC分类号： H03K19096

CPC分类号： H03K19/00338 ,  H03K19/096

摘要： A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

公开(公告)号：US06351151B2

公开(公告)日：2002-02-26

申请号：US09909104

申请日：2001-07-18

申请人： Sudarshan Kumar ,  Wenjie Jiang

发明人： Sudarshan Kumar ,  Wenjie Jiang

IPC分类号： H03K19096

CPC分类号： H03K19/00338 ,  H03K19/096

摘要： A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

摘要翻译： 一种降低动态电路软错误的技术。 对于一个实施例，动态电路包括具有输出节点的动态逻辑门，在该输出节点检测逻辑门的逻辑输出值。 耦合到输出节点的保持器电路被配置为通过增加输出节点处的临界电荷来硬化动态电路。

公开(公告)号：US20120307739A1

公开(公告)日：2012-12-06

申请号：US13579220

申请日：2011-02-24

申请人： Koichi Ishihara ,  Yasushi Takatori ,  Yusuke Asai ,  Riichi Kudo ,  Wenjie Jiang ,  Tomoyuki Yamada ,  Masato Mizoguchi

发明人： Koichi Ishihara ,  Yasushi Takatori ,  Yusuke Asai ,  Riichi Kudo ,  Wenjie Jiang ,  Tomoyuki Yamada ,  Masato Mizoguchi

IPC分类号： H04W4/00

CPC分类号： H04B7/0691 ,  H04B7/0452 ,  H04B7/0834 ,  H04B7/0874 ,  H04B7/0877 ,  H04B7/10

摘要： A spatial multiplexing wireless transmission system is formed by a base station, and by a plurality of terminal stations that are provided with a plurality of antennas. The base station is provided with an information signal generating portion, a control signal generating portion, a transmission frame generating portion, a multiple beamforming portion, a transmission/reception switching portion, a reception signal processing portion, a propagation environment estimating portion, and an antenna information generating portion. At least one of the terminal stations is provided with a transmission/reception switching portion, a reception signal processing portion, a decoding portion, an antenna information extracting portion, an antenna information generating portion, an transmitting portion, a battery, a remaining battery detecting portion, a transmission request extracting portion, and a propagation environment estimating portion.

摘要翻译： 空间复用无线传输系统由基站和多个设置有多个天线的终端站形成。 基站设置有信息信号生成部，控制信号生成部，发送帧生成部，多波束形成部，发送接收切换部，接收信号处理部，传播环境估计部以及 天线信息生成部。 至少一个终端站设置有发送/接收转换部分，接收信号处理部分，解码部分，天线信息提取部分，天线信息产生部分，发送部分，电池，剩余电池检测 传输请求提取部分和传播环境估计部分。

公开(公告)号：US08891555B2

公开(公告)日：2014-11-18

申请号：US13579220

申请日：2011-02-24

申请人： Koichi Ishihara ,  Yasushi Takatori ,  Yusuke Asai ,  Riichi Kudo ,  Wenjie Jiang ,  Tomoyuki Yamada ,  Masato Mizoguchi

发明人： Koichi Ishihara ,  Yasushi Takatori ,  Yusuke Asai ,  Riichi Kudo ,  Wenjie Jiang ,  Tomoyuki Yamada ,  Masato Mizoguchi

IPC分类号： H04J3/24 ,  H04B7/06 ,  H04B7/08 ,  H04B7/04 ,  H04B7/10

CPC分类号： H04B7/0691 ,  H04B7/0452 ,  H04B7/0834 ,  H04B7/0874 ,  H04B7/0877 ,  H04B7/10

摘要： A spatial multiplexing wireless transmission system is formed by a base station, and by a plurality of terminal stations that are provided with a plurality of antennas. The base station is provided with an information signal generating portion, a control signal generating portion, a transmission frame generating portion, a multiple beamforming portion, a transmission/reception switching portion, a reception signal processing portion, a propagation environment estimating portion, and an antenna information generating portion. At least one of the terminal stations is provided with a transmission/reception switching portion, a reception signal processing portion, a decoding portion, an antenna information extracting portion, an antenna information generating portion, an transmitting portion, a battery, a remaining battery detecting portion, a transmission request extracting portion, and a propagation environment estimating portion.

摘要翻译： 空间复用无线传输系统由基站和多个设置有多个天线的终端站形成。 基站设置有信息信号生成部，控制信号生成部，发送帧生成部，多波束形成部，发送接收切换部，接收信号处理部，传播环境估计部以及 天线信息生成部。 至少一个终端站设置有发送/接收转换部分，接收信号处理部分，解码部分，天线信息提取部分，天线信息产生部分，发送部分，电池，剩余电池检测 传输请求提取部分和传播环境估计部分。