公开(公告)号：US20140033158A1

公开(公告)日：2014-01-30

申请号：US14043689

申请日：2013-10-01

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co., Ltd.

Inventor： Fong-Yuan Chang ,  Wei-Shun Chuang ,  Sheng-Hsiung Chen ,  Hsian-Ho Chang ,  Ruey-Shi Rau

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A computer implemented method for routing a net includes selecting, using one or more computer systems, a first spine routing track from a first multitude of routing tracks in accordance with a first cost function, and further in accordance with data associated with the net and the first multitude of routing tracks. The method further includes generating, using one or more computer systems, a first spine wire on the selected first spine routing track.

Abstract translation: 用于路由网络的计算机实现的方法包括：根据第一成本函数，以及根据与所述网络和所述网络相关联的数据，使用一个或多个计算机系统来选择来自第一多个路由轨道的第一脊线路由轨道 第一批路由轨道。 该方法还包括使用一个或多个计算机系统在所选择的第一脊线路由轨道上生成第一脊线。

公开(公告)号：US09305127B2

公开(公告)日：2016-04-05

申请号：US14541555

申请日：2014-11-14

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Wei-Cheng Chen ,  Jen-Feng Huang

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: In one or more embodiments, a caching apparatus includes functionality to persist evaluation results associated with pcells in a design across sessions of an EDA application as well as across design libraries. The caching apparatus may create and maintain a mirror cache in a design library with only subMasters referenced by the design library. The contents of a central cache file or a mirror cache in the design library are examined for an evaluation result. If the evaluation result is not found in the central cache file, the evaluation result may be retrieved from the mirror cache if present.

Abstract translation: 在一个或多个实施例中，高速缓存设备包括在EDA应用程序的跨会话以及跨设计库中的设计中持续与pcell相关联的评估结果的功能。 缓存设备可以在设计库中创建和维护镜像缓存，只有设计库引用的subMasters。 检查设计库中的中央缓存文件或镜像缓存的内容以进行评估结果。 如果在中央缓存文件中没有找到评估结果，则可以从镜像缓存中检索评估结果（如果存在）。

公开(公告)号：US20150278421A1

公开(公告)日：2015-10-01

申请号：US14576108

申请日：2014-12-18

Applicant: SYNOPSYS TAIWAN CO., LTD.

Inventor： HSIEN-SHIH CHIU ,  KAI-SHUN HU

IPC: G06F17/50 ,  H01L23/498

CPC classification number: G06F17/5077 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/16225

Abstract: A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.

Abstract translation: 用于路由具有凸块焊盘阵列的电路装置的方法包括识别与凸块相关联的布线方向，基于布线方向产生电源带和接地带，根据路由方向形成路由信道，设置 路线通道中的起始点和端点，并使用路由通道内的线连接起始点和端点。 该方法还包括响应于目标功率/接地比将起点放置在电源或接地带上。

公开(公告)号：US20150178441A1

公开(公告)日：2015-06-25

申请号：US14576117

申请日：2014-12-18

Applicant: SYNOPSYS TAIWAN CO., LTD.

Inventor： HSIEN-SHIH CHIU ,  KAI-SHUN HU

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077

Abstract: A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in the adjacent objects that overlap with the expanded segment. For each of the identified regions, an expanded region is formed, which has a shape and size to enclose the identified object with additional spacing around the perimeter. Next, the size of the expanded segment is reduced to form the wide segment such that the wide segment does not overlap any of the adjacent expanded objects.

Abstract translation: 一种用于设计集成电路（IC）的方法部分地包括将设置在IC中的线分成多个段，每个段具有从第一端点延伸到第二端点的长度。 然后，每个段被加宽而不重叠任何相邻的对象。 作为示例，形成包括第一端点和第二端点的中间或扩展段，并且具有与相邻对象重叠的尺寸。 该方法包括识别与扩展段重叠的相邻对象中的区域。 对于每个所识别的区域，形成了扩展区域，其具有形状和尺寸，以围绕周边具有附加间隔来包围所识别的对象。 接下来，扩展段的尺寸减小以形成宽段，使得宽段不与任何相邻的扩展对象重叠。

公开(公告)号：US09003350B2

公开(公告)日：2015-04-07

申请号：US14043689

申请日：2013-10-01

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Fong-Yuan Chang ,  Wei-Shun Chuang ,  Sheng-Hsiung Chen ,  Hsian-Ho Chang ,  Ruey-Shi Rau

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A computer implemented method for routing a net includes selecting, using one or more computer systems, a first spine routing track from a first multitude of routing tracks in accordance with a first cost function, and further in accordance with data associated with the net and the first multitude of routing tracks. The method further includes generating, using one or more computer systems, a first spine wire on the selected first spine routing track.

Abstract translation: 用于路由网络的计算机实现的方法包括：根据第一成本函数，以及根据与所述网络和所述网络相关联的数据，使用一个或多个计算机系统来选择来自第一多个路由轨道的第一脊线路由轨道 第一批路由轨道。 该方法还包括使用一个或多个计算机系统在所选择的第一脊线路由轨道上生成第一脊线。

公开(公告)号：US08990756B2

公开(公告)日：2015-03-24

申请号：US14086158

申请日：2013-11-21

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Hsin-Po Wang ,  Song Yuan ,  Hung-Shih Wang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A computer-implemented method for routing at least one conductor includes generating the at least one conductor within a bounded region on a planar surface in accordance with a template, and placing at least one slit in the conductor when the conductor overlaps a specified region of the bounded region in accordance with a specified pattern.

Abstract translation: 用于布线至少一个导体的计算机实现的方法包括根据模板在平坦表面上的有界区域内生成至少一个导体，并且当导体与导体重叠在一个特定的区域时，在导体中放置至少一个狭缝 有界区域按照指定的模式。

公开(公告)号：US20150067626A1

公开(公告)日：2015-03-05

申请号：US14476320

申请日：2014-09-03

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Tung-Chieh CHEN ,  Po-Hsun WU ,  Po-Hung LIN ,  Tsung-Yi HO

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5063 ,  G06F17/5072 ,  G06F17/5081

Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.

Abstract translation: 用于生成设计布局的计算机实现的方法包括调用计算机以接收设计的示意图，生成与设计相关联的连接图，将连接图与存储在数据库中的多个连接图进行比较，并选择 在生成设计布局时与匹配连接图相关联的布局。

公开(公告)号：US20140351777A1

公开(公告)日：2014-11-27

申请号：US14452368

申请日：2014-08-05

Applicant: Synopsys Taiwan Co., Ltd.

Inventor： Yingtsai Chang ,  Sweyyan Shei ,  Hung-Chun Chiu ,  Meng-Chyi Lin ,  Hwa Mao ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027

Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file.

Abstract translation: 提出了一种仿真电路设计的系统。 该系统包括通过仿真接口耦合到现场可编程门阵列（FPGA）的主机工作站，其被配置为当主机工作站被调用以验证电路设计时仿真和验证电路设计。 仿真接口被配置为提供用于至少验证的定时和控制信息。 该系统还包括包括指令的计算机可读存储介质，当执行时，使计算机编译电路设计的一部分，以及适于配置FPGA的相关联的验证模块。 编译符合一个描述文件。

公开(公告)号：US08832615B2

公开(公告)日：2014-09-09

申请号：US13891062

申请日：2013-05-09

Applicant: Synopsys, Inc. ,  Synopsys Taiwan Co. Ltd.

Inventor： Ming Han Hsieh ,  Chih-Neng Hsu ,  Ming-Hui Hsieh

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/78

Abstract: A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window.

Abstract translation: 一种用于检测低功率IC模拟中的信号行为异常的方法，包括接收IC的电路设计和功率规格，根据功率规格确定至少一个功率序列检验规则，模拟电路设计和功率规格 以获得转储文件，基于所述转储文件识别所述至少一个功率序列检查规则的至少一个异常，以及生成与所识别的所述至少一个功率序列检查规则的异常相关的信息。 该方法还包括通过在波​​形窗口中显示与异常相关联的不正常信号的波形以及电路设计的一部分和/或与该异常相关联的功率规范的一部分来设置调试器中的上下文以调试异常 在文本窗口中出现异常。

公开(公告)号：US08782588B2

公开(公告)日：2014-07-15

申请号：US14043619

申请日：2013-10-01

Applicant: Synopsys Taiwan Co., Ltd. ,  Synopsys, Inc.

Inventor： Fong-Yuan Chang ,  Wei-Shun Chuang ,  Sheng-Hsiung Chen ,  Hsian-Ho Chang ,  Ruey-Shi Rau

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A computer implemented method for routing a net includes generating, using one or more computer systems, a first wire associated with the net in accordance with data associated with the net including a multitude of pins and partitioning, using the one or more computer systems, the multitude of pins into at least a first group of pins in accordance with a first cost function. The method further includes connecting, using the one or more computer systems, a second wire associated with the first group of pins to the first wire, and connecting, using the one or more computer systems, a third wire from a pin of the first group of pins to the second wire.

Abstract translation: 用于路由网络的计算机实现的方法包括：使用一个或多个计算机系统，使用一个或多个计算机系统，根据与所述网络相关联的数据，使用一个或多个计算机系统来生成与所述网络相关联的第一线路，所述网络包括多个引脚和分区， 根据第一成本函数将多个引脚插入到至少第一组引脚中。 该方法还包括使用一个或多个计算机系统将与第一组引脚相关联的第二线连接到第一线，以及使用一个或多个计算机系统从第一组的引脚连接第三线 的针脚到第二根线。