CIRCUIT AND METHOD TO CONTROL SLEW RATE OF A CURRENT-MODE LOGIC OUTPUT DRIVER
    21.
    发明申请
    CIRCUIT AND METHOD TO CONTROL SLEW RATE OF A CURRENT-MODE LOGIC OUTPUT DRIVER 有权
    用于控制电流模式逻辑输出驱动器的电流的电路和方法

    公开(公告)号:US20120299616A1

    公开(公告)日:2012-11-29

    申请号:US13114479

    申请日:2011-05-24

    CPC classification number: H03K5/01 H04L25/0272 H04L25/0282

    Abstract: A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.

    Abstract translation: 提供了一种至少根据数据传输的速度选择多个转换速率控制设置中的至少一个并接收以数据传输速度接收输入数据的输入数据的方法。 该方法还包括根据所选择的多个转换速率控制设置中的至少一个切换所接收的输入数据,并以数据传输速度发送输出数据。 还提供了数据驱动器装置,其包括至少一个包括一个或多个转换速率控制的激活部分,电压模式驱动器部分和至少第一电流模式驱动器部分。 还提供了一种用数据编码的计算机可读存储设备,用于使制造设施适配以创建数据驱动器设备。 还提供了包括数据驱动器装置,数据存储装置和处理器装置的系统。

    Network management providing network health information and lockdown security
    22.
    发明授权
    Network management providing network health information and lockdown security 有权
    网络管理提供网络健康信息和锁定安全

    公开(公告)号:US08316438B1

    公开(公告)日:2012-11-20

    申请号:US11696638

    申请日:2007-04-04

    CPC classification number: H04L12/66

    Abstract: Network management to establish and maintain the health and security of a computing network, such as a home network. A network management tool may identify the media access control (MAC) address for each device in the network, and allow a user to identify which devices are authorized to be a member of the network. If the network gateway device supports MAC address filtering, a user can then employ the network management tool to configure the router to exclude non-authorized devices from joining or remaining in the network based upon their MAC addresses. Further, the network management tool may allow a user to configure a wireless gateway device to stop broadcasting its service set identifier (SSID), change the SSID, or both, identify to the user when a wireless gateway device is using encryption, and, if so, what type of encryption. Still further, the tool may monitor the status of various software applications on devices in the network, and then alert a user if the status of any of the devices in the network requires attention. Further, the network management tool may provide recommendations to a user for correcting or changing the status of the monitored software applications.

    Abstract translation: 网络管理建立和维护计算网络的健康和安全性,如家庭网络。 网络管理工具可以识别网络中每个设备的媒体访问控制(MAC)地址,并允许用户识别哪些设备被授权为网络的成员。 如果网络网关设备支持MAC地址过滤,则用户可以使用网络管理工具来配置路由器,以根据其MAC地址来排除非授权设备加入或保留在网络中。 此外,网络管理工具可以允许用户配置无线网关设备以在无线网关设备正在使用加密时停止广播其服务集标识符(SSID),改变SSID或两者,以向用户识别,并且如果 那么,什么类型的加密。 此外,该工具可以监视网络中的设备上的各种软件应用的状态,然后向用户通知网络中任何设备的状态是否需要注意。 此外,网络管理工具可以向用户提供用于校正或改变所监视的软件应用的状态的建议。

    System and method for quantitative imaging of chemical composition to decompose more than two materials
    23.
    发明授权
    System and method for quantitative imaging of chemical composition to decompose more than two materials 有权
    用于化学成分定量成像分解两种以上材料的系统和方法

    公开(公告)号:US08290232B2

    公开(公告)日:2012-10-16

    申请号:US12371425

    申请日:2009-02-13

    Abstract: A system and method for decomposing more than two materials in an imaging object includes performing a CT imaging acquisition of a portion of an imaging object using at least two energy levels to acquire imaging data associated with each of the at least two energy levels. A total mass attenuation of the imaging data is expressed as a weighted sum of constituent element mass attenuation coefficients and an effective atomic number and density of the constituent elements in the portion of the imaging object is determined by one of a number of methods. Accordingly, concentration of the constituent elements in imaged object is determined by solve the expression using known material attenuation coefficients and the measured CT data.

    Abstract translation: 用于在成像对象中分解两种以上材料的系统和方法包括使用至少两个能级来执行对成像对象的一部分的CT成像采集,以获取与所述至少两个能级中的每一个相关联的成像数据。 成像数据的总质量衰减表示为构成元素质量衰减系数的加权和,并且成像对象的该部分中的组成元素的有效原子数和密度由多种方法之一确定。 因此,通过使用已知材料衰减系数和测量的CT数据求解表达式来确定成像对象中的组成元素的浓度。

    Electrostatic discharge power clamp trigger circuit using low stress voltage devices
    25.
    发明授权
    Electrostatic discharge power clamp trigger circuit using low stress voltage devices 有权
    静电放电电源钳位触发电路采用低应力电压器件

    公开(公告)号:US08102632B2

    公开(公告)日:2012-01-24

    申请号:US12406684

    申请日:2009-03-18

    CPC classification number: H03K19/00315

    Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.

    Abstract translation: 描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。 位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路,以保护IC免受过多的电源电压和ESD电压的影响。 每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。 实施例的保护电路包括高电压IO引脚接口,耦合到IO引脚的电压降网络,并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平, 耦合在所述电压降网络和接地端子之间的NMOS分流晶体管,以及耦合到所述NMOS分流晶体管的触发电路,以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。

    METHOD FOR ENTERING AN IDLE MODE
    26.
    发明申请
    METHOD FOR ENTERING AN IDLE MODE 有权
    进入空闲模式的方法

    公开(公告)号:US20110188426A1

    公开(公告)日:2011-08-04

    申请号:US13054897

    申请日:2008-12-19

    CPC classification number: H04W12/06 H04W60/00 H04W68/00 H04W76/27

    Abstract: A method for entering an idle mode, which is used in a Worldwide Interoperability for Microwave Access system, comprising: during the procedure of a terminal enter to idle mode from active mode, an paging agent of the terminal sending mobility restriction parameters of the terminal to a mobility restriction parameter storage network element; the mobility restriction parameter storage network element saving the mobility restriction parameters; the mobility restriction parameter storage network element being an anchor paging controller, or an anchor authenticator, or a function entity including a function of the anchor paging controller and a function of the anchor authenticator. to save the mobility restriction parameters of a terminal when the terminal enters an idle mode may be achieved by using the method of the present invention, so that a mobility restriction judgment is performed to the terminal in the subsequent process procedure, and the problem of erroneously allowing the terminal to quit from the idle mode and enter an active mode or to update its location when the terminal is in the non-authorized regions can be avoided.

    Abstract translation: 一种在全球互通微波接入系统中使用的进入空闲模式的方法,包括:在终端进入空闲模式的过程中,终端的寻呼机发送终端的移动性限制参数, 移动性限制参数存储网元; 移动限制参数存储网元保存移动性限制参数; 移动性限制参数存储网元作为主寻呼控制器,或锚定认证器,或者包括锚寻呼控制器的功能的功能实体和锚定认证器的功能。 当终端进入空闲模式时,为了节省终端的移动性限制参数,可以通过使用本发明的方法来实现,从而在随后的处理过程中对终端执行移动性限制判断,并且存在错误的问题 允许终端从空闲模式退出并进入活动模式或者当终端在非授权区域时可以更新其位置。

    METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS
    27.
    发明申请
    METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS 有权
    用于测量高速串行链路的相位锁定环带宽度参数的方法

    公开(公告)号:US20100246739A1

    公开(公告)日:2010-09-30

    申请号:US12410413

    申请日:2009-03-24

    CPC classification number: H03L7/08 H04L7/033

    Abstract: A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator, determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.

    Abstract translation: 一种用于测量高速串行链路的锁相环带宽参数的方法包括以下步骤:利用频率发生器启动等于参考频率的锁相环的时钟输入的抖动频率,确定参考抖动振幅值 基准频率下的波形分析器的锁相环的时钟输出,参考抖动幅度值是参考频率时钟输出的时间间隔误差抖动趋势的函数; 并且通过频率发生器调整时钟输入的抖动频率,直到时钟输出的经调整的抖动幅度值达到由波形分析器确定的目标值,调整后的抖动幅度是时钟的时间间隔误差趋势的函数 以调整频率输出。

    Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices
    29.
    发明申请
    Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices 有权
    使用低应力电压器件的静电放电电源钳位触发电路

    公开(公告)号:US20100238598A1

    公开(公告)日:2010-09-23

    申请号:US12406684

    申请日:2009-03-18

    CPC classification number: H03K19/00315

    Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.

    Abstract translation: 描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。 位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路,以保护IC免受过多的电源电压和ESD电压的影响。 每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。 实施例的保护电路包括高电压IO引脚接口,耦合到IO引脚的电压降网络,并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平, 耦合在所述电压降网络和接地端子之间的NMOS分流晶体管,以及耦合到所述NMOS分流晶体管的触发电路,以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。

    Digitally compensated highly stable holdover clock generation techniques using adaptive filtering
    30.
    发明授权
    Digitally compensated highly stable holdover clock generation techniques using adaptive filtering 有权
    使用自适应滤波的数字补偿高度稳定的保持时钟生成技术

    公开(公告)号:US07692499B2

    公开(公告)日:2010-04-06

    申请号:US12006368

    申请日:2007-12-31

    CPC classification number: H03L7/093 H03L1/02 H03L7/099 H03L7/0996 H03L7/235

    Abstract: A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

    Abstract translation: 提出了利用集成电路和外部OCXO产生高度稳定的保持时钟的系统和方法。 集成电路包括输入参考时钟接收器,相位和频率检测器,其在输入参考时钟信号和反馈时钟信号之间产生误差信号,存储模型参数以预测OCXO的频率变化的数据存储块,适应性 滤波模块,其包括数字环路滤波器和用于更新模型参数并且基于该模型预测频率变化的算法,使得系统能够在正常或保持模式下操作的开关,数字控制振荡器和反馈分频器的开关。

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