公开(公告)号：US08115569B2

公开(公告)日：2012-02-14

申请号：US12561727

申请日：2009-09-17

申请人： Kiejin Lee ,  Jong Chel Kim ,  Young Soo Jang

发明人： Kiejin Lee ,  Jong Chel Kim ,  Young Soo Jang

IPC分类号： H01P1/213 ,  H01P1/202

CPC分类号： H01P1/2136 ,  H01P1/2056

摘要： Disclosed herein is a monoblock dielectric multiplexer capable of processing multi-band signals. The monoblock dielectric multiplexer includes a dielectric block implemented as a hexahedral dielectric forming a body of the monoblock dielectric multiplexer. An external electrode is applied to an external surface of the dielectric block except for to a top surface. Resonant holes are each formed in a cylindrical shape and formed through the top surface and a bottom surface of the dielectric block. Internal electrodes are respectively formed on inner walls of the resonant holes. A plurality of capacitance patterns is formed on the top surface of the dielectric block and is configured to surround corresponding resonant holes. Input/output electrode units are formed and spaced apart from the capacitance patterns and configured to form capacitance coupling to the capacitance patterns. A common antenna stage is formed in a center portion of the dielectric block.

摘要翻译： 这里公开了能够处理多频带信号的单块介质多路复用器。 单块介质多路复用器包括实现为形成单块介质多路复用器的主体的六面体电介质的介质块。 将外部电极施加到介电块的外表面，除了顶表面。 谐振孔各自形成为圆柱形并通过介电块的顶表面和底表面形成。 内部电极分别形成在谐振孔的内壁上。 多个电容图案形成在介质块的顶表面上并被构造成围绕相应的共振孔。 输入/输出电极单元形成并与电容图案间隔开并且被配置成形成耦合到电容图案的电容。 在介质块的中心部分形成共同的天线级。

公开(公告)号：US08018356B2

公开(公告)日：2011-09-13

申请号：US12678253

申请日：2008-09-10

申请人： Na Young Kim ,  Young Soo Jang

发明人： Na Young Kim ,  Young Soo Jang

IPC分类号： H03M7/00

CPC分类号： G11B20/1833 ,  G11B7/0065 ,  G11B2220/2504 ,  H03M13/2909

摘要： According to an embodiment of the present invention, a data encoding method includes separating an input sequence into a plurality of n-bit blocks, wherein n is a natural number, and converting each of the n-bit blocks into a block code including M rows and N columns such that every bit in the block code has at least one identical bit adjacent horizontally or vertically to the bit, wherein M and N are natural numbers.

摘要翻译： 根据本发明的实施例，一种数据编码方法包括将输入序列分离成多个n位块，其中n是自然数，并且将每个n位块转换成包括M行的块码 和N列，使得块码中的每个位具有与该位水平或垂直相邻的至少一个相同位，其中M和N是自然数。

公开(公告)号：US07854916B2

公开(公告)日：2010-12-21

申请号：US11989856

申请日：2006-08-01

申请人： Sei-Ung Park ,  Choong-Hoon Paik ,  Ju-Suk Ryu ,  Seong-Jae Lim ,  Jin-Soo Baik ,  Young-Soo Jang

发明人： Sei-Ung Park ,  Choong-Hoon Paik ,  Ju-Suk Ryu ,  Seong-Jae Lim ,  Jin-Soo Baik ,  Young-Soo Jang

IPC分类号： C01G23/00 ,  C01F11/02

CPC分类号： C01G23/006 ,  C01P2004/03 ,  C01P2006/42 ,  C04B35/4682 ,  C04B35/6265 ,  C04B35/62655 ,  C04B35/62675 ,  C04B35/6268 ,  C04B2235/528 ,  C04B2235/5409 ,  C04B2235/5445 ,  C04B2235/72 ,  C04B2235/77 ,  C04B2235/79

摘要： The present invention relates to a hydrothermal synthesis for preparing barium titanate powder as the essential material for a multi-layer ceramic capacitor. The object of the invention is to prepare barium titanate powder having high purity, particle size of submicron order, uniform particle distribution and excellent crystallinity, by reacting hydrous titanic acid compound prepared via sulfuric acid process with crystalline titanium oxide and barium hydroxide, as the starting material, at a temperature between 60° C. and 300° C. under a pressure between 5 Kgf/cm2 and 50 Kgf/cm2. The process for preparing barium titanate according to the present invention provides barium titanate powder having Ba/Ti molar ratio of 1.000±0.002 and high purity by applying calcination under reductive condition to the solid product obtained from hydrous titanic acid compound prepared via sulfuric acid process with crystalline titanium oxide and barium hydroxide, as the starting substances, to convert barium sulfate, which was produced from residual sulfide in the raw material, to barium titanate.

摘要翻译： 本发明涉及一种制备钛酸钡粉末作为多层陶瓷电容器的基本材料的水热合成方法。 本发明的目的是通过使通过硫酸方法制备的含水钛酸化合物与结晶二氧化钛和氢氧化钡作为起始物来制备具有高纯度，亚微米级数，亚微米粒径分布和优异结晶度的钛酸钡粉末 材料，在5kgf / cm 2至50Kgf / cm 2之间的压力下在60℃至300℃的温度下进行。 根据本发明的制备钛酸钡的方法通过在还原条件下对从通过硫酸方法制备的含水钛酸化合物获得的固体产物进行煅烧，提供具有1.000±0.002的Ba / Ti摩尔比的钛酸钡粉末和高纯度， 结晶二氧化钛和氢氧化钡作为起始物质，将由原料中的残留硫化物生成的硫酸钡转化为钛酸钡。

公开(公告)号：US20090097834A1

公开(公告)日：2009-04-16

申请号：US12287736

申请日：2008-10-14

申请人： Young-soo Jang ,  Jung-su Kim

发明人： Young-soo Jang ,  Jung-su Kim

IPC分类号： G03B17/00 ,  H04N5/228

CPC分类号： G03B17/00 ,  H04N5/2253 ,  H04N5/23248

摘要： Provided is a shake correction module including: a base plate; a first movable slider member for accommodating an imaging device; a first drive portion for moving the first slider member in a first axis direction; a second movable slider member coupled with the first slider member; a second drive portion for moving the second slider member in a second axis direction; a support member attached to the base plate for pressing the first and second slider members toward the base plate; a first ferromagnetic support bearing between the base plate and the first slide member; and a second ferromagnetic support bearing between the first slider member and the second slider member. The module further includes at least one magnet for centering the first and second ferromagnetic support bearings in respective first and second bearing grooves that may be formed on the base plate and the first and second sliding members.

摘要翻译： 提供了一种抖动校正模块，包括：基板; 用于容纳成像装置的第一可移动滑动构件; 用于沿第一轴线方向移动第一滑动构件的第一驱动部分; 与所述第一滑动构件联接的第二可移动滑动构件; 第二驱动部，用于沿第二轴线方向移动所述第二滑动构件; 支撑构件，其附接到所述基板，用于将所述第一和第二滑动构件朝向所述基板按压; 在所述基板和所述第一滑动构件之间的第一铁磁支撑轴承; 以及在第一滑动构件和第二滑动构件之间的第二铁磁支撑轴承。 模块还包括至少一个磁体，用于使第一和第二铁磁性支撑轴承居中在可以形成在基板和第一和第二滑动构件上的相应的第一和第二轴承槽中。

公开(公告)号：US06392275B1

公开(公告)日：2002-05-21

申请号：US09421681

申请日：1999-10-20

申请人： Young-soo Jang

发明人： Young-soo Jang

IPC分类号： H01L2976

CPC分类号： H01L29/66659 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0615 ,  H01L29/7322 ,  H01L29/7835

摘要： A semiconductor device having a substrate composed of a DMOS transistor, a complementary MOS (CMOS) transistor and a bipolar junction transistor is disclosed. A highly-doped bottom layer is formed on a lower edge of a body region of the DMOS transistor, a heavily doped bottom layer of a conductivity type opposite to that of the substrate is formed on a lower edge of source and drain regions of the CMOS transistor, and a highly-doped bottom layer of the same conductivity type as that of the substrate is formed on a lower portion of an intrinsic base region of the bipolar junction transistor, to thereby enhance the electrical characteristics of devices.

摘要翻译： 公开了具有由DMOS晶体管，互补MOS（CMOS）晶体管和双极结型晶体管组成的衬底的半导体器件。 在DMOS晶体管的主体区域的下边缘上形成高度掺杂的底层，在CMOS的源极和漏极区域的下边缘处形成与衬底相反的导电类型的重掺杂底层 晶体管，并且在双极结型晶体管的本征基极区域的下部形成与衬底相同的导电类型的高度掺杂的底层，从而增强器件的电气特性。

公开(公告)号：US5707721A

公开(公告)日：1998-01-13

申请号：US711047

申请日：1996-09-10

申请人： Young-Soo Jang

发明人： Young-Soo Jang

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/42376 ,  H01L29/7833 ,  H01L29/7834

摘要： Methods of forming field effect transistors having oxidation-controlled gate lengths include the steps of forming an insulated gate electrode on a face of semiconductor substrate. The gate electrode has exposed ends thereof which define an initial gate length. Source and drain region dopants are then implanted into first portions of the face, using the insulated gate electrode as an implant mask. The implanted first portions of the face and the exposed ends of the insulated gate electrode are then thermally oxidized to form a relatively thick oxide layer. During this step, the implanted dopants are diffused and bird's beak oxide extensions are formed at the upper and bottom corners of the gate electrode. The bird's beak oxide extensions are preferably formed to increase the separation distance between the gate electrode and the source and drain regions and thereby reduce the gate-source/drain capacitance and inhibit parasitic hot electron injection from the drain region. The step of thermally oxidizing the exposed ends of the insulated gate electrode also causes the ends to be consumed and the first portions of the face to become recessed. Thus, during oxidation, the length of the gate electrode can be reduced in a controlled manner and the degree of vertical overlap between the gate electrode and the diffused source and drain region dopants can be reduced to obtain a further reduction in the parasitic gate-source/drain capacitance. In addition, gate lengths having sub-micron dimensions can be achieved without requiring sub-micron photolithographic line widths to define the gate electrode.

摘要翻译： 形成具有氧化控制的栅极长度的场效应晶体管的方法包括在半导体衬底的表面上形成绝缘栅电极的步骤。 栅电极具有限定初始栅极长度的露出端。 然后使用绝缘栅电极作为植入物掩模将源区和漏区掺杂剂注入到面的第一部分中。 然后，将表面的注入的第一部分和绝缘栅电极的暴露端热氧化以形成相对较厚的氧化物层。 在该步骤期间，注入的掺杂剂被扩散，并且在栅电极的上角和下角形成鸟喙氧化物延伸部。 鸟嘴状氧化物延伸部优选地形成为增加栅极电极和源极区域与漏极区域之间的间隔距离，从而减小栅极 - 源极/漏极电容并且抑制从漏极区域发出的寄生热电子注入。 热氧化绝缘栅电极的露出端的步骤也使得端部被消耗，并且面部的第一部分变得凹陷。 因此，在氧化期间，可以以受控的方式减小栅电极的长度，并且可以减小栅电极和扩散源极和漏区掺杂剂之间的垂直重叠程度，以进一步减小寄生栅极源 /漏极电容。 此外，可以实现具有亚微米尺寸的栅极长度，而不需要亚微米光刻线宽度来限定栅电极。