公开(公告)号：US20140372722A1

公开(公告)日：2014-12-18

申请号：US13916722

申请日：2013-06-13

Applicant: ARM Limited

Inventor： Oskar Flordal ,  Hakan Persson ,  Andreas Engh-Halstvedt

IPC: G06F12/02

CPC classification number: G06F12/02 ,  G06F9/5016 ,  G06F12/0284 ,  G06T1/60

Abstract: A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocator 40 needing to know the sizes of the results being produced by the processing cores.

Abstract translation: 处理系统包括多个处理核和用于将任务分配给处理核的任务分配器。 处理核心执行分配给它们的任务，以产生任务的结果，结果由处理核心存储在缓冲区中。 任务分配器向处理核心指示缓冲器内存储结果的内存部分。 当处理核心确定给定的存储器部分变满时，处理核心请求任务分配器指示在其中存储其结果的新的存储器部分。 处理系统允许任务分配器动态且有效地将存储器部分分配给多个处理核，而任务分配器40需要知道由处理核产生的结果的大小。

公开(公告)号：US11010959B2

公开(公告)日：2021-05-18

申请号：US15497129

申请日：2017-04-25

Applicant: ARM Limited

Inventor： Sandeep Kakarlapudi ,  Andreas Engh-Halstvedt ,  Samuel Martin ,  Edvard Fielding

IPC: G06T15/20 ,  G09G5/373 ,  G06F3/01 ,  G06T1/20 ,  G06T15/00 ,  G06T15/04 ,  G06T17/05 ,  G06T17/10 ,  G06T19/20 ,  G09G5/14 ,  G06T1/60 ,  G06T11/40

Abstract: When performing foveated rendering, a graphics processor is controlled to render plural, e.g. three, different resolution versions from the same viewpoint for a scene. The rendered different resolution images are then appropriately combined (composited) to provide the output “foveated” image (output frame) that is displayed.
The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.

公开(公告)号：US20170316601A1

公开(公告)日：2017-11-02

申请号：US15497129

申请日：2017-04-25

Applicant: ARM Limited

Inventor： Sandeep Kakarlapudi ,  Andreas Engh-Halstvedt ,  Samuel Martin ,  Edvard Fielding

IPC: G06T15/20 ,  G06T19/20 ,  G06T17/10 ,  G06T17/05 ,  G06T15/04 ,  G06F3/01 ,  G09G5/14 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40

CPC classification number: G06T15/205 ,  G06F3/01 ,  G06F3/011 ,  G06F3/013 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T17/05 ,  G06T17/10 ,  G06T19/20 ,  G06T2210/36 ,  G09G5/14 ,  G09G5/373 ,  G09G2310/04 ,  G09G2360/122

Abstract: When performing foveated rendering, a graphics processor is controlled to render plural, e.g. three, different resolution versions from the same viewpoint for a scene. The rendered different resolution images are then appropriately combined (composited) to provide the output “foveated” image (output frame) that is displayed.The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.

公开(公告)号：US09767595B2

公开(公告)日：2017-09-19

申请号：US13875822

申请日：2013-05-02

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Sandeep Kakarlapudi ,  Michael Stokes

IPC: G06T15/50 ,  G06T15/00

CPC classification number: G06T15/005

Abstract: A tile-based graphics processing pipeline 1 comprising a rasteriser 3, a renderer 6, a tile buffer 10, a write out stage 13 and a programmable processing stage 14. The tile buffer 10 stores multiple render targets for a deferred shading operation and the programmable processing stage 14 is operable to, under the control of graphics program instructions, read data from two or more of a set of multiple render targets for a deferred shading operation stored in the tile buffer 10, perform a deferred shading processing operation using the read data, and to write the result of the processing operation to an output render target in the tile buffer 10, or to external memory.

公开(公告)号：US20170004005A1

公开(公告)日：2017-01-05

申请号：US15125661

申请日：2015-03-11

Applicant: ARM LIMITED

Inventor： Robert Elliott ,  Vatsalya Prasad ,  Andreas Engh-Halstvedt

IPC: G06F9/48 ,  G06F9/54

CPC classification number: G06F9/4812 ,  G06F9/542

Abstract: A microprocessor system (1) includes a host processor (2),a graphics processing unit (GPU) (3) that includes a number of processing cores (4), and an exception handler. When a thread that is executing on a processing core (4) encounters an exception in its instruction sequence, the thread is redirected to the exception handler. However, the exception event is also communicated to a task manager (5) of the GPU 3. The task manager (5) then broadcasts a cause exception message to each processing core (4). Each processing core then identifies the threads that it is currently executing that the cause exception message relates to, and redirects those threads to the exception handler. In this way, an exception caused by a single thread is broadcast to all threads within a task.

Abstract translation: 微处理器系统（1）包括主处理器（2），包括多个处理核心（4）的图形处理单元（GPU）（3）和异常处理器。 当在处理核心（4）上执行的线程在其指令序列中遇到异常时，线程被重定向到异常处理程序。 然而，异常事件也被传送给GPU3的任务管理器（5）。然后任务管理器（5）向每个处理核心（4）广播原因异常消息。 每个处理核心然后标识它当前正在执行的原因异常消息所关联的线程，并将这些线程重定向到异常处理程序。 以这种方式，单个线程导致的异常被广播到任务内的所有线程。

公开(公告)号：US09070200B2

公开(公告)日：2015-06-30

申请号：US13875831

申请日：2013-05-02

Applicant: ARM Limited

Inventor： Andreas Engh-Halstvedt

IPC: G06F13/00 ,  G06T1/20 ,  G09G5/39

CPC classification number: G06T1/20 ,  G06T11/40 ,  G09G5/02 ,  G09G5/39 ,  G09G2360/122 ,  G09G2360/127

Abstract: A tile-based graphics processing system comprises a host processor 1 and a graphics processing pipeline 3. The graphics processing pipeline 3 includes a rasterizer, a renderer, a tile buffer comprising an allocated amount of memory for use as the tile buffer, and a write out stage configured to write data stored in the tile buffer to an external memory. The driver 4 for the graphics processing pipeline 3 on the host processor 1 determines the tile data storage requirements for each render target to be generated for a render output to be generated by the graphics processing system and allocates portions of the memory allocated for use as the tile buffer to respective ones of the render targets based on the determination.

Abstract translation: 基于瓦片的图形处理系统包括主机处理器1和图形处理流水线3.图形处理流水线3包括光栅化器，渲染器，包括分配的存储器量用作瓦片缓冲器的瓦片缓冲器，以及写入 输出级被配置为将存储在瓦片缓冲器中的数据写入外部存储器。 用于主机处理器1上的图形处理流水线3的驱动器4确定要由图形处理系统生成的渲染输出生成的每个渲染目标的瓦片数据存储需求，并且将分配用于作为 基于该确定，将缓冲区分配给各个渲染目标。

公开(公告)号：US08922572B2

公开(公告)日：2014-12-30

申请号：US13623751

申请日：2012-09-20

Applicant: ARM Limited

Inventor： Frode Heggelund ,  Aske Simon Christensen ,  Andreas Engh-Halstvedt

IPC: G06F13/00 ,  G06T1/00 ,  G06F15/16 ,  G06T15/00 ,  G09G5/36 ,  G06T15/40 ,  G06T1/20 ,  G06T11/40

CPC classification number: G06T1/20 ,  G06T1/00 ,  G06T11/40

Abstract: The fragment processing pipeline 10 of a graphics processing core 2 has an associated occlusion query cache 19 that is used to maintain a set of local occlusion counters 21. The occlusion query cache 19 is maintained in a local memory 3 of the graphics processing system and can communicate via an interconnect 7 with a set of master occlusion counters 22 in a main memory 5 for the graphics processing system. When an occlusion query starts, a corresponding occlusion counter 22 is initialised in the main memory 5. A corresponding local occlusion counter 21 is also provided in the occlusion query cache 19 in the local memory 3 of the graphics processor, and is used to count the results of the occlusion query. The local occlusion counter value is written back to the occlusion counter 22 for the query in the main memory 5 at the appropriate time for further processing.

Abstract translation: 图形处理核心2的片段处理流水线10具有关联的遮挡查询高速缓存19，其用于维护一组局部遮挡计数器21.遮挡查询高速缓存19被保存在图形处理系统的本地存储器3中，并且可以 通过互连7与用于图形处理系统的主存储器5中的一组主遮挡计数器22进行通信。 当闭塞查询开始时，在主存储器5中初始化对应的遮挡计数器22.在图形处理器的本地存储器3中的遮挡查询高速缓存19中还提供相应的局部遮挡计数器21，并且用于计数 闭塞查询的结果。 局部遮挡计数器值在适当的时间被写回到主存储器5中的查询的遮挡计数器22用于进一步处理。

公开(公告)号：US20140327671A1

公开(公告)日：2014-11-06

申请号：US13875822

申请日：2013-05-02

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Sandeep Kakarlapudi ,  Michael Stokes

IPC: G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005

Abstract: A tile-based graphics processing pipeline 1 comprising a rasteriser 3, a renderer 6, a tile buffer 10, a write out stage 13 and a programmable processing stage 14. The tile buffer 10 stores multiple render targets for a deferred shading operation and the programmable processing stage 14 is operable to, under the control of graphics program instructions, read data from two or more of a set of multiple render targets for a deferred shading operation stored in the tile buffer 10, perform a deferred shading processing operation using the read data, and to write the result of the processing operation to an output render target in the tile buffer 10, or to external memory.

Abstract translation: 包括光栅化器3，渲染器6，瓦片缓冲器10，写入级13和可编程处理级14的基于瓦片的图形处理流水线1.瓦片缓冲器10存储用于延迟着色操作和可编程 处理阶段14可操作以在图形程序指令的控制下从存储在瓦片缓冲器10中的延迟着色操作的一组多个渲染目标中的两个或更多个读取数据，使用读取的数据执行延迟着色处理操作 并将处理操作的结果写入瓦片缓冲器10中的输出渲染目标，或写入外部存储器。

公开(公告)号：US20140152683A1

公开(公告)日：2014-06-05

申请号：US13690151

申请日：2012-11-30

Applicant: ARM LIMITED

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Edvard Sorgard ,  Thomas Jeremy Olson ,  Marius Bjorge

IPC: G06T11/00

CPC classification number: G06T15/04 ,  G06T1/60

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. If the texture page that is required for performing a texturing operation at an originally desired level of detail (52) is not present in the local memory of the graphics processing system (53), the virtual texture lookup process loops back to try to sample the texture at an increased level of detail (55), and so on, until texture data that can be used is found in the local memory of the graphics processing system (53). This allows the texturing operation to proceed using texture data for the texel positions in question from a higher level (less detailed) mipmap in place of the originally desired texture data.

Abstract translation: 图形虚拟纹理系统，其中存储在主机系统的存储介质中的纹理被划分为相应的页面，然后将其加载到图形处理系统的本地存储器中以供使用。 如果在图形处理系统（53）的本地存储器中不存在用于以最初期望的细节级（52）执行纹理化操作所需的纹理页面，则虚拟纹理查找过程循环回来以尝试对 纹理处于增加的细节水平（55），等等，直到在图形处理系统（53）的本地存储器中找到可以使用的纹理数据。 这允许纹理化操作从较高级别（较不详细的）mipmap继续使用所讨论的纹素位置的纹理数据来代替原始期望的纹理数据。