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公开(公告)号：US11561882B2
公开(公告)日：2023-01-24
申请号：US16332130
申请日：2017-08-09
Applicant: ARM LIMITED
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , John Michael Horley , Michael John Williams , Michael John Gibbs
Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence. The sequence may include a branch behaviour setting instruction that indicates an identified instruction within the sequence, where execution of the branch behaviour setting instruction enables a branch behaviour to be associated with the identified instruction that causes the processing circuitry to branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in the sequence. The trace generation circuitry is further arranged to generate, from the instruction execution information, a trace element indicative of execution behaviour of the branch behaviour setting instruction, and a trace element to indicate that the branch behaviour has been triggered on encountering the identified instruction within the sequence. This enables a very efficient form of trace stream to be used even in situations where the instruction sequence executed by the processing circuitry includes such branch behaviour setting instructions.
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22.发明授权公开(公告)号：US11294787B2
公开(公告)日：2022-04-05
申请号：US16321503
申请日：2017-08-10
Applicant: ARM LIMITED
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , John Michael Horley , Michael John Williams
Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being notified to the trigger signal generation circuitry. This allows the monitoring of particular program instruction execution behaviour to be qualified so that the processing circuitry is only notified if in addition a qualifying event is determined to be present.
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公开(公告)号：US10394557B2
公开(公告)日：2019-08-27
申请号：US15538365
申请日：2015-11-23
Applicant: ARM LIMITED
Inventor： Stephan Diestelhorst , Michael John Williams , Richard Roy Grisenthwaite , Matthew James Horsnell
Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.
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公开(公告)号：US10140476B2
公开(公告)日：2018-11-27
申请号：US15189284
申请日：2016-06-22
Applicant: ARM LIMITED
Inventor： John Michael Horley , Michael John Williams , Simon John Craske , Uma Maheswari Ramalingam
IPC: G06F21/74
Abstract: A data processing apparatus comprises a processing element having associated memory storage and one or more registers, the processing element being configured to perform processing activities in two or more security modes so as to inhibit a processing activity performed in one of the security modes from accessing at least some information associated with a processing activity performed in another of the security modes; in which the processing element is configured, in response to a function call causing a branch from a processing activity in a first security mode to a processing activity in a second security mode, to store the contents of one or more of the registers in the memory storage and, in response to a branch return to the first security mode, to retrieve the register contents from the memory storage; and trace apparatus configured to generate items of trace data indicative of processing activities of the processing element; in which the trace apparatus is configured to detect a branch return operation by the processing element and to generate one or more items of trace data relating to the branch return operation; and in which the trace apparatus is configured to detect the processing element retrieving register contents from the memory storage in response to a branch return to the first security mode and to generate one or more further items of trace data relating to the retrieval of the register contents from the memory storage.
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公开(公告)号：US09798646B2
公开(公告)日：2017-10-24
申请号：US14747141
申请日：2015-06-23
Applicant: ARM LIMITED
Inventor： Michael John Williams , Simon John Craske
CPC classification number: G06F11/348 , G06F11/1484 , G06F11/301 , G06F11/3024 , G06F11/3409 , G06F11/3433 , G06F11/3466 , G06F2201/815 , G06F2201/86 , G06F2201/88
Abstract: A data processing apparatus has processing circuitry which can execute instructions at one of several privilege levels. A plurality of performance monitoring circuits are included. In response to an instruction executed at a first privilege level, first configuration data can be set for controlling performance monitoring by a first subset of performance monitoring circuits. A disable control flag can be set in response to an instruction executed at a second privilege level higher than the first privilege level. If the disable control flag has a predetermined value then performance monitoring control circuitry disables performance monitoring by the first subset of performance monitoring circuits while the processing circuitry is executing instructions at the second privilege level.
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Patent Agency Ranking
公开(公告)号：US12147325B2
公开(公告)日：2024-11-19
申请号：US16305184
申请日：2017-05-15
Applicant: ARM LIMITED
Inventor： Michael John Williams
Abstract: Statistical sampling of diagnostic data within an apparatus for processing data 2 is performed based upon sample interval monitoring and address monitoring. A program instruction has its diagnostic data stored when it meets a sample interval criteria and an address match criteria. The address match may correspond to an instruction address of the program instruction or a target address to be read or written by the program instruction.
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公开(公告)号：US11461104B2
公开(公告)日：2022-10-04
申请号：US14952807
申请日：2015-11-25
Applicant: ARM LIMITED
Inventor： Michael John Williams , Richard Roy Grisenthwaite , Simon John Craske
Abstract: Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.
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公开(公告)号：US11080106B2
公开(公告)日：2021-08-03
申请号：US15066453
申请日：2016-03-10
Applicant: ARM LIMITED
Inventor： Michael John Williams , Simon John Craske
IPC: G06F9/54
Abstract: In an apparatus performing multi-threaded data processing event handling circuitry receives event information from the data processing circuitry indicative of an event which has occurred during the data processing operations. Visibility configuration storage holds a set of visibility configuration values, each visibility configuration value associated with a thread of the multiple threads and the event handling circuitry adapts its use of the event information to restrict visibility of the event information for software of threads other than the thread which generated the event information when a visibility configuration value for the thread which generated the event information has a predetermined value. This allows multi-threaded event monitoring to be supported, whilst protecting event information from a particular thread for which it is desired to limit its visibility to software of other threads.
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29.发明授权公开(公告)号：US11048617B2
公开(公告)日：2021-06-29
申请号：US16971415
申请日：2019-01-17
Applicant: Arm Limited
Inventor： Michael John Williams , Graeme Peter Barnes , John Michael Horley
IPC: G06F11/36
Abstract: A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items. The number of metadata items accessed by each instance of the metadata access operation is non-deterministic by the debugger from the metadata access operation. However, the at least one command is such that the plurality of instances of the metadata access operation are performed by the processing circuitry without the debugger interrogating the processing circuitry between each instance of the metadata access operation to determine progress in the number of metadata items accessed. Such an approach can significantly improve the efficiency of performing such accesses to metadata items under debugger control.
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公开(公告)号：US11036616B2
公开(公告)日：2021-06-15
申请号：US15008569
申请日：2016-01-28
Applicant: ARM LIMITED
Inventor： Michael John Williams , John Michael Horley
Abstract: An apparatus for generating a trace stream, a method for generating a trace stream, an apparatus for receiving a trace stream and a method of receiving a trace stream are provided. Header items and payload items in the trace stream are respectively grouped together into a contiguous sequence of header items and a contiguous sequence of payload items. This can for example facilitate the production of a trace stream in which the trace stream is aligned to a predetermined length (e.g. corresponding to an alignment of a memory in which the trace stream is to be stored) thus facilitating its interpretation.
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