公开(公告)号：US11775297B2

公开(公告)日：2023-10-03

申请号：US16651045

申请日：2018-08-21

Applicant: Arm Limited

Inventor： Grigorios Magklis ,  Matthew James Horsnell ,  Stephan Diestelhorst

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/30021 ,  G06F9/30058 ,  G06F9/30076 ,  G06F9/30094 ,  G06F9/3842 ,  G06F9/467

Abstract: In a system providing transactional memory support, a transaction nesting depth testing instruction is provided for triggering processing circuitry 4 to set at least one status value to one of a plurality of states depending on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth is 1 and at least one further state selected when the transaction nesting depth is greater than or less than 1. The supported ISA enables the setting of the at least one status value and a conditional branch conditional on the at least one status value being in the first state to be performed in response to a single transaction nesting depth testing instruction and a single conditional branch instruction.

公开(公告)号：US10394557B2

公开(公告)日：2019-08-27

申请号：US15538365

申请日：2015-11-23

Applicant: ARM LIMITED

Inventor： Stephan Diestelhorst ,  Michael John Williams ,  Richard Roy Grisenthwaite ,  Matthew James Horsnell

IPC: G06F9/30 ,  G06F11/36 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F12/08 ,  G06F12/126

Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.

公开(公告)号：US20190018786A1

公开(公告)日：2019-01-17

申请号：US15819378

申请日：2017-11-21

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Stephan Diestelhorst

IPC: G06F12/1009 ,  G06F12/109 ,  G06F12/1045 ,  G06F12/084

CPC classification number: G06F12/1009 ,  G06F12/082 ,  G06F12/084 ,  G06F12/1063 ,  G06F12/109 ,  G06F2212/283 ,  G06F2212/621 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682

Abstract: A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.

公开(公告)号：US10002020B2

公开(公告)日：2018-06-19

申请号：US15325301

申请日：2015-06-09

Applicant: ARM LIMITED

Inventor： Matthew James Horsnell ,  Stephan Diestelhorst

IPC: G06F9/46 ,  G06F12/128 ,  G06F9/52 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0811

CPC classification number: G06F9/467 ,  G06F9/528 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/128 ,  G06F2212/1032 ,  G06F2212/451 ,  G06F2212/621

Abstract: A data processing apparatus and method of data processing are provided, which relate to the operation of a processor which maintains a call stack in dependence on the data processing instructions executed. The processor is configured to operate in a transactional execution mode when the data processing instructions seek access to a stored data item which is shared with a further processor. When the processor enters its transactional execution mode it stores a copy of the current stack depth indication and thereafter, when operating in its transactional execution mode, further modifications to the call stack are compared to the copy of the stack depth indication stored. If the relative stacking position of the required modification is in a positive stack growth direction with respect to the copy stored, the modification to the call stack is labelled as non-speculative. Conversely if the modification to the call stack is to be made at a relative stacking position which is not in a positive growth direction with respect to the position indicated by the copy stored, then that modification is labelled as speculative. The size of the write-set associated with maintaining the call stack while in transactional execution mode can therefore be reduced.

公开(公告)号：US11657003B2

公开(公告)日：2023-05-23

申请号：US16778040

申请日：2020-01-31

Applicant: Arm Limited

Inventor： Ilias Vougioukas ,  Nikos Nikoleris ,  Andreas Lars Sandberg ,  Stephan Diestelhorst

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1027 ,  G06N5/04 ,  G06F9/48

CPC classification number: G06F12/1036 ,  G06F9/4806 ,  G06F12/1027 ,  G06N5/04 ,  G06F2212/681

Abstract: Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and control circuitry to control the transfer of at least a subset of the translation data from the translation lookaside buffer associated with a first processing device to the translation lookaside buffer associated with a second, different, processing device.

公开(公告)号：US11481290B2

公开(公告)日：2022-10-25

申请号：US17046396

申请日：2019-04-08

Applicant: Arm Limited

Inventor： Matthew James Horsnell ,  Grigorios Magklis ,  Stephan Diestelhorst

IPC: G06F11/00 ,  G06F11/14 ,  G06F9/46 ,  G06F11/07

Abstract: An apparatus and a method of operating a data processing apparatus, and simulators thereof, are disclosed. Data processing circuitry performs data processing operations in response to instructions, where some sets of instructions may be defined as a transaction which are to be performed atomically with respect to other operations performed by the data processing circuitry. When a synchronous exception occurs during a transaction the transaction is aborted and an exception counter is incremented. When the counter reaches a threshold value a transaction failure signal is generated, allowing, if appropriate a response to this number of exceptions causing transaction aborts to be carried out.

公开(公告)号：US10929308B2

公开(公告)日：2021-02-23

申请号：US16169206

申请日：2018-10-24

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Nikos Nikoleris ,  Prakash S. Ramrakhyani ,  Stephan Diestelhorst

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/0808 ,  G06F12/06 ,  G06F3/06 ,  G06F13/16

Abstract: There is provided an apparatus that includes an input port to receive, from a requester, any one of: a lookup operation comprising an input address, and a maintenance operation. Maintenance queue circuitry stores a maintenance queue of at least one maintenance operation and address storage stores a translation between the input address and an output address in an output address space. In response to receiving the input address, the output address is provided in dependence on the maintenance queue. In response to storing the maintenance operation, the maintenance queue circuitry causes an acknowledgement to be sent to the requester. By providing a separate maintenance queue for performing the maintenance operation, there is no need for a requester to be blocked while maintenance is performed.

公开(公告)号：US10908944B2

公开(公告)日：2021-02-02

申请号：US15532221

申请日：2015-11-24

Applicant: ARM Limited

Inventor： Stephan Diestelhorst ,  Matthew James Horsnell ,  Guy Larri

IPC: G06F9/455 ,  G06F9/46 ,  G06F9/38

Abstract: An apparatus (2) with multiple processing elements (4, 6, 8) has shared transactional processing resources (10, 50, 75) for supporting processing of transactions, which comprise operations performed speculatively following a transaction start event whose results are committed following a transaction end event. The transactional processing resources may have a significant overhead and sharing these between the processing elements helps reduce energy consumption and circuit area.

公开(公告)号：US20190129871A1

公开(公告)日：2019-05-02

申请号：US15881937

申请日：2018-01-29

Applicant: Arm Limited

Inventor： Alejandro Rico Carro ,  Pavel Shamis ,  Stephan Diestelhorst

IPC: G06F13/16 ,  G06F12/084 ,  G06F12/0871 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1642 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0871 ,  G06F12/0888 ,  G06F13/4086 ,  G06F13/4234 ,  G06F2212/1024 ,  G06F2212/254 ,  G06F2212/284 ,  G06F2212/604 ,  H04L45/745 ,  H04L47/2433 ,  H04L49/10 ,  H04L67/2852

Abstract: A method and apparatus are provided for assigning transport priorities to messages in a data processing system. An incoming message at an input/output (I/O) interface of the data processing system includes a message identifier and payload data. Match information, including an indicator or whether the message identifier of the incoming message matches an identifier of a request in a receive queue (RQ), is used to assign a transport priority value to the incoming message. The incoming message is transported to the destination node through an interconnect structure dependent upon the assigned transport priority value.

公开(公告)号：US10795815B2

公开(公告)日：2020-10-06

申请号：US15166458

申请日：2016-05-27

Applicant: ARM Limited

Inventor： Jonathan Curtis Beard ,  Wendy Elsasser ,  Stephan Diestelhorst

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/08 ,  G06F15/78 ,  G06F9/38

Abstract: A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.