Self referenced single-ended chip to chip communication

    公开(公告)号:US10756849B2

    公开(公告)日:2020-08-25

    申请号:US16253100

    申请日:2019-01-21

    Applicant: Apple Inc.

    Abstract: A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

    CHIP TO CHIP INTERFACE WITH SCALABLE BANDWIDTH

    公开(公告)号:US20200183874A1

    公开(公告)日:2020-06-11

    申请号:US16700356

    申请日:2019-12-02

    Applicant: Apple Inc.

    Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.

    On-Chip Parameter Measurement
    23.
    发明申请

    公开(公告)号:US20170089975A1

    公开(公告)日:2017-03-30

    申请号:US14868954

    申请日:2015-09-29

    Applicant: Apple Inc.

    Abstract: An apparatus and method for performing on-chip parameter measurement is disclosed. In one embodiment, an IC includes a number of functional circuit blocks each having one or more sensors for measuring parameters such as voltage and temperature. Each of the functional blocks includes circuitry coupled to receive power from a local supply voltage node. Similarly, the circuitry in each of the sensors is also coupled to receive power from the corresponding local supply voltage node. Each of the sensors may be calibrated to compensate for process, voltage, and temperature variations. Various methods based on characterization of the sensors may be used to perform the calibrations.

    Shunt Integrated Voltage Regulator
    24.
    发明申请
    Shunt Integrated Voltage Regulator 有权
    并联集成稳压器

    公开(公告)号:US20150222182A1

    公开(公告)日:2015-08-06

    申请号:US14287931

    申请日:2014-05-27

    Applicant: Apple Inc.

    Abstract: A method and apparatus for augmenting an external voltage regulator with a shunt integrated voltage regulator is disclosed. In one embodiment, an integrated circuit (IC) includes a load circuit coupled to a supply voltage node. The supply voltage node is electrically coupled to receive a supply voltage from an external voltage regulator. The IC also includes a shunt integrated voltage regulator coupled to the supply voltage node and implemented on the same IC die as the load circuit. If the supply voltage falls below a specified value (e.g., to increased current demand), the integrated voltage regulator may begin supplying current to the load. This may cause the supply voltage to return to within its specified range of the specified value, while allowing the external voltage regulator sufficient time to respond to the increased current demand. Thus, voltage droops on the supply voltage node may be minimized.

    Abstract translation: 公开了一种用于利用分流集成稳压器增强外部电压调节器的方法和装置。 在一个实施例中,集成电路(IC)包括耦合到电源电压节点的负载电路。 电源节点电耦合以从外部电压调节器接收电源电压。 IC还包括耦合到电源电压节点并在与负载电路相同的IC管芯上实现的分流集成稳压器。 如果电源电压低于指定值(例如,增加电流需求),集成稳压器可能开始向负载提供电流。 这可能导致电源电压恢复到指定值的指定范围内,同时允许外部电压调节器有足够的时间来响应增加的电流需求。 因此,电源电压节点上的电压下降可以被最小化。

Patent Agency Ranking