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公开(公告)号：US20230283449A1
公开(公告)日：2023-09-07
申请号：US18313729
申请日：2023-05-08
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
CPC classification number: H04L7/0079 , H04L7/0016 , H04L25/03878
Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
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公开(公告)号：US11750325B2
公开(公告)日：2023-09-05
申请号：US16933449
申请日：2020-07-20
Applicant: Apple Inc.
Inventor： Jafar Savoj , Praveen R. Singh , Brian S. Leibowitz , Emerson S. Fang
IPC: H04L1/02 , H03K19/0175 , H04L25/02 , H04L25/06 , H04L25/03
CPC classification number: H04L1/02 , H03K19/0175 , H04L25/0272 , H04L25/062 , H04L2025/03363
Abstract: A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.
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公开(公告)号：US11528016B2
公开(公告)日：2022-12-13
申请号：US17154699
申请日：2021-01-21
Applicant: Apple Inc.
Inventor： Mehrdad Heshami , Jafar Savoj
IPC: H03K5/00 , H03K3/0233 , H03K5/1536 , H03K5/1532
Abstract: A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.
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公开(公告)号：US20220231672A1
公开(公告)日：2022-07-21
申请号：US17154699
申请日：2021-01-21
Applicant: Apple Inc.
Inventor： Mehrdad Heshami , Jafar Savoj
IPC: H03K3/0233
Abstract: A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.
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公开(公告)号：US11023403B2
公开(公告)日：2021-06-01
申请号：US16700356
申请日：2019-12-02
Applicant: Apple Inc.
Inventor： Jafar Savoj , Jose A. Tierno , Sanjeev K. Maheshwari , Brian S. Leibowitz , Pradeep R. Trivedi , Gin Yee , Emerson S. Fang
Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.
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Patent Agency Ranking
公开(公告)号：US11005457B2
公开(公告)日：2021-05-11
申请号：US16006750
申请日：2018-06-12
Applicant: Apple Inc.
Inventor： Ramy A. Ahmed , Amr A. Hafez , Jafar Savoj
Abstract: A circuit that produces an output signal having a frequency that is proportional to absolute temperature (PTAT) is disclosed. In one embodiment, the circuit includes a ring oscillator and a bias current circuit coupled thereto. The ring oscillator and the bias current circuit are implemented in close proximity to one another. During operation, the bias current circuit generates a bias current that is provided to the ring oscillator. The amount of bias current generated is dependent upon the temperature of the circuit. In turn, the frequency of an output signal provided by the ring oscillator is dependent on the amount of bias current received from the bias current circuit. Accordingly, the frequency of the ring oscillator output signal is dependent on the temperature of the circuit.
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公开(公告)号：US10459478B1
公开(公告)日：2019-10-29
申请号：US15953019
申请日：2018-04-13
Applicant: Apple Inc.
Inventor： Jafar Savoj , Amr A. Hafez , Ramy A. Ahmed
IPC: G01K13/00 , G06F1/10 , G11C19/28 , H03K3/03 , G01R19/165
Abstract: A sensor circuit and integrated circuit having the same is disclosed. In one embodiment, a sensor circuit includes first and second ring oscillators having different circuit topologies. A first counter is coupled to receive an output signal from the first ring oscillator, while a second counter is coupled to receive an output signal from the second ring oscillator. The sensor circuit further includes a local clock circuit that provides a clock signal to the first and second counters. Furthermore, the local clock circuit is coupled to provide the clock signal exclusively to circuitry within the sensor circuit, the circuitry including the first and second counters.
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8.发明授权公开(公告)号：US11868109B2
公开(公告)日：2024-01-09
申请号：US17466320
申请日：2021-09-03
Applicant: Apple Inc.
Inventor： Robert S. Brandt, II , Bruno W. Garlepp , Ke Yun , Navin Kumar , Jafar Savoj
IPC: G05B19/042 , G06F13/38
CPC classification number: G05B19/042 , G06F13/387 , G05B2219/25341
Abstract: A universally-designed control circuit for communicating with multiple types of sensors is disclosed. For example, a control circuit may communicate with either ring oscillator-based sensors or BJT-based sensors based on programming implemented in the control circuit. The control circuit may include programmable communication protocol circuits for communicating with the sensors and conversion circuits that convert a particular type of sensor data packet into a generic format. The generic format sensor data may then be utilized by a power management unit or other device to control operation of an integrated circuit.
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公开(公告)号：US20230092906A1
公开(公告)日：2023-03-23
申请号：US17482302
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
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公开(公告)号：US11586240B1
公开(公告)日：2023-02-21
申请号：US17867117
申请日：2022-07-18
Applicant: Apple Inc.
Inventor： Bo Sun , Brian S. Leibowitz , Jafar Savoj , Sanjeev K. Maheshwari
Abstract: Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.
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