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    On-chip parameter measurement
    3.
    发明授权
    On-chip parameter measurement 有权

    公开(公告)号：US09720033B2

    公开(公告)日：2017-08-01

    申请号：US14868954

    申请日：2015-09-29

    Applicant: Apple Inc.

    Inventor： Jafar Savoj ,  Brian S. Leibowitz ,  Emerson S. Fang

    IPC: G01R31/28 ,  G01R35/00

    CPC classification number: G01R31/2874 ,  G01R31/2884 ,  G01R31/30 ,  G01R35/005 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3203 ,  H03K19/003

    Abstract: An apparatus and method for performing on-chip parameter measurement is disclosed. In one embodiment, an IC includes a number of functional circuit blocks each having one or more sensors for measuring parameters such as voltage and temperature. Each of the functional blocks includes circuitry coupled to receive power from a local supply voltage node. Similarly, the circuitry in each of the sensors is also coupled to receive power from the corresponding local supply voltage node. Each of the sensors may be calibrated to compensate for process, voltage, and temperature variations. Various methods based on characterization of the sensors may be used to perform the calibrations.

    SELF REFERENCED SINGLE-ENDED CHIP TO CHIP COMMUNICATION
    4.
    发明申请
    SELF REFERENCED SINGLE-ENDED CHIP TO CHIP COMMUNICATION 审中-公开

    公开(公告)号：US20200235856A1

    公开(公告)日：2020-07-23

    申请号：US16253100

    申请日：2019-01-21

    Applicant: Apple Inc.

    Inventor： Jafar Savoj ,  Praveen R. Singh ,  Brian S. Leibowitz ,  Emerson S. Fang

    IPC: H04L1/02 ,  H03K19/0175

    Abstract: A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

    Chip to chip interface with scalable bandwidth
    5.
    发明授权
    Chip to chip interface with scalable bandwidth 有权

    公开(公告)号：US10521391B1

    公开(公告)日：2019-12-31

    申请号：US16204252

    申请日：2018-11-29

    Applicant: Apple Inc.

    Inventor： Jafar Savoj ,  Jose A. Tierno ,  Sanjeev K. Maheshwari ,  Brian S. Leibowitz ,  Pradeep R. Trivedi ,  Gin Yee ,  Emerson S. Fang

    IPC: G06F13/42 ,  G06F9/52 ,  G06F13/40

    Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.

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