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公开(公告)号：US20220261252A1
公开(公告)日：2022-08-18
申请号：US17175150
申请日：2021-02-12
申请人： Arm Limited
摘要： Circuitry comprises prediction storage to store, for a given branch operation, a multi-bit data item and indicator data defining a subset of bits of the multi-bit data item, the subset being one of an ordered succession of different subsets of bits of the multi-bit data item; and prediction generator circuitry to generate a predicted branch outcome for the given branch operation in dependence upon the subset of bits defined by the indicator data and, in response to generation of the predicted branch outcome, to change the subset of bits defined by the indicator data to a next subset in the ordered succession of subsets.
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公开(公告)号：US20200285476A1
公开(公告)日：2020-09-10
申请号：US16292454
申请日：2019-03-05
申请人： Arm Limited
摘要： An apparatus and method are provided for handling prediction information. The apparatus has processing circuitry for performing data processing operations in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction comprising a sequence of instructions. Prediction circuitry is used to generate predictions in relation to instruction flow changing instructions, and prediction storage is provided to store a plurality of items of prediction information that are referenced by the prediction circuitry when generating the predictions. The items of prediction information maintained by the prediction storage change based on the instructions being executed by the processing circuitry. A recovery storage is activated by the transactional memory support circuitry at a transaction start point to store a restore pointer identifying a chosen location in the prediction storage. Between the transaction start point and the transaction end point, the recovery storage receives any item of prediction information removed from the prediction storage that was present in the prediction storage at the transaction start point. In response to the transaction being aborted, the restore pointer is used in order to discard from the prediction storage any items of prediction information added to the prediction storage after the transaction start point, and in addition any items of prediction information stored in the recovery storage are stored back into the prediction storage. This can significantly improve prediction accuracy in systems that may need to retry transactions due to a transaction abort, without requiring the entire prediction storage state to be captured at the transaction start point.
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公开(公告)号：US20200057643A1
公开(公告)日：2020-02-20
申请号：US16105028
申请日：2018-08-20
申请人： Arm Limited
IPC分类号： G06F9/38
摘要： An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry for executing instructions out-of-order with respect to original program order, and event counting prediction circuitry for maintaining event count values for branch instructions, for use in making branch outcome predictions for those branch instructions. Further, checkpointing storage stores state information of the apparatus at a plurality of checkpoints to enable the state information to be restored for a determined one of those checkpoints in response to a flush event. The event counting prediction circuitry has training storage with a first number of training entries, each training entry being associated with a branch instruction. The event counting prediction circuitry implements a training phase for each training entry during which it seeks to determine an event count value for the associated branch instruction based on branch outcome behaviour of the branch instruction observed for instances of execution of the branch instruction that have been committed by the processing circuitry. The event counting prediction circuitry further has access storage with a second number of active entries, where the second number is less than the first number. Each active entry is associated with a branch instruction for which an event count value has been successfully determined during the training phase. The event counting prediction circuitry is arranged to make branch outcome predictions for branch instructions having an active entry. At each checkpoint, state information for the active entries is stored to the checkpointing storage. This provides a particularly efficient form of event counting prediction circuitry that can be used in out-of-order systems, while reducing the amount of state information that needs to stored into the checkpointing storage at each checkpoint.
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公开(公告)号：US20190258485A1
公开(公告)日：2019-08-22
申请号：US15900914
申请日：2018-02-21
申请人： Arm Limited
IPC分类号： G06F9/30
摘要： An apparatus is provided to perform branch prediction in respect of a plurality of instructions divided into a plurality of blocks. Receiving circuitry receives references to at least two blocks in the plurality of blocks. Branch prediction circuitry performs at least two branch predictions at a time. The branch predictions are performed in respect of the at least two blocks and the at least two blocks are non-contiguous.
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公开(公告)号：US20190138315A1
公开(公告)日：2019-05-09
申请号：US15806605
申请日：2017-11-08
申请人： Arm Limited
摘要： Program flow prediction circuitry comprises a history register to store history data for at least one or more most recently executed branch instructions; a memory to store a plurality of sets of weight values, one set for each of a group of portions of one or more bits of the history data; access circuitry to access, for a current branch instruction to be predicted, a weight value for each of the portions of one or more bits of the history data by selecting from the set of weight values in dependence upon a current value of the portions of the history data; a combiner to generate a combined weight value by combining the weight values accessed by the access circuitry; a comparator to compare the combined weight value with a prediction threshold value to detect whether or not a branch represented by the current branch instruction is predicted to be taken; and weight modifier circuitry to modify the accessed weight values in dependence upon a resolution of whether the branch represented by the current branch instruction is taken or not.
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公开(公告)号：US20170344492A1
公开(公告)日：2017-11-30
申请号：US15592529
申请日：2017-05-11
申请人： ARM Limited
IPC分类号： G06F12/1027 , G06F12/1009
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/657 , G06F2212/684
摘要： A memory management unit 22, 34, 48 serves to use first stage of address translation and permission data S1 managed by a guest operating system and second stage of address translation and permission data S2 managed by a hypervisor. If there is a mismatch between the permissions (or other characteristics) provided by these different translation and permission data sets, then a speculative mismatch response is triggered. This speculative mismatch response may comprise storing a virtual address to intermediate physical address mapping within a cache 32, 36 within the memory management unit. Such a cache can subsequently be accessed by an instruction seeking to determine an intermediate physical address associated with a mismatch without having to wait for a full translation (page table walk) operation to be performed.
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