公开(公告)号：US20180196673A1

公开(公告)日：2018-07-12

申请号：US15741303

申请日：2016-06-23

Applicant: ARM Limited

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS ,  Alejandro MARTINEZ VICENTE ,  Nathanael PREMILLIEU

IPC: G06F9/30

Abstract: A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.

公开(公告)号：US20240354105A1

公开(公告)日：2024-10-24

申请号：US18762800

申请日：2024-07-03

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Jacob EAPEN ,  Mbou EYOLE

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036

Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying, independently of the vector length, one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within a result vector of data elements that also contains data elements from a second vector. Since the control data in the at least one control register identifies the data elements to be extracted without reference to the vector length, this provides a great deal of flexibility as to how the data elements to be extracted may be selected within the first vector.

公开(公告)号：US20230273792A1

公开(公告)日：2023-08-31

申请号：US18006813

申请日：2021-07-08

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  David Hennah MANSELL ,  Richard Roy GRISENTHWAITE ,  Matthew Lucien EVANS ,  Jelena MILANOVIC

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30036

Abstract: Instruction decoder to decode processing instructions; one or more first registers; first processing circuitry to execute the decoded processing instructions in a first processing mode and configured to execute the decoded processing instructions using the one or more first registers; and control circuitry to execute the decoded processing instructions in a second processing mode using one or more second registers; the instruction decoder being configured to decode processing instructions selected from a first instruction set and a second instruction set in the second processing mode, in which one or both of the first and second instruction sets comprises at least one unique instruction set; the instruction decoder configured to decode one or more mode change instructions to change between the first and second processing mode; and the first processing circuitry configured to change the current processing mode between the first and second processing mode responding to executing mode change instruction.

公开(公告)号：US20210042114A1

公开(公告)日：2021-02-11

申请号：US16531206

申请日：2019-08-05

Applicant: Arm Limited

Inventor： David Hennah MANSELL ,  Nigel John STEPHENS ,  Matthew Lucien EVANS

IPC: G06F9/30 ,  G06F9/38

Abstract: A data processing apparatus is provided comprising: a plurality of storage circuits to store data. Execution circuitry performs one or more operations using the storage circuits in response to instructions. The instructions include a relinquish instruction. The execution circuitry responds to the relinquish instruction by indicating that at least one of the plurality of storage circuits is an unused storage circuit and the execution circuitry affects execution of future instructions based on the unused storage circuit after executing the relinquish instruction.

公开(公告)号：US20210034362A1

公开(公告)日：2021-02-04

申请号：US16975486

申请日：2019-02-15

Applicant: Arm Limited

Inventor： Michael John WILLIAMS ,  Nigel John STEPHENS

IPC: G06F9/30

Abstract: Data processing apparatus comprises vector processing circuitry to selectively apply vector processing operations defined by vector processing instructions to generate one or more data elements of a data vector comprising a plurality of data elements at respective data element positions of the data vector, according to the state of respective predicate flags associated with the positions of the data vector; and generator circuitry to generate instruction sample data indicative of processing activities of the vector processing circuitry for selected ones of the vector processing instructions, instruction sample data indicating at least the state of the predicate flags at execution of the selected vector processing instructions.

公开(公告)号：US20180253310A1

公开(公告)日：2018-09-06

申请号：US15759914

申请日：2016-09-05

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F9/30043 ,  G06F9/30036 ,  G06F9/3013 ,  G06F11/073 ,  G06F11/0793 ,  G06F15/8061

Abstract: First and second types of vector load instruction are provided. For the first type, a response action is performed when an exceptional condition is detected for a load operation performed for a first active data element of at least one vector register, but when the exceptional condition is detected for an active data element other than the first active data element, the response action is suppressed and element identifying information is stored identifying the element which caused the exceptional condition. For the second type, the response action is suppressed and the element identifying information is stored when the exceptional condition arises for any active data element. This approach is useful for allowing loop speculation and loop unrolling to be used together to improve performance of vectorised code.

公开(公告)号：US20180210733A1

公开(公告)日：2018-07-26

申请号：US15745478

申请日：2016-06-15

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Jacob EAPEN ,  Mbou EYOLE

IPC: G06F9/30

CPC classification number: G06F9/30192 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within sequential data element positions of the result vector starting from a first end of the result vector, and data elements from a second vector are output to the remaining result vector data element positions not occupied by the extracted data elements from the first vector.

公开(公告)号：US20180210731A1

公开(公告)日：2018-07-26

申请号：US15743735

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Mbou EYOLE ,  Alejandro MARTINEZ VICENTE

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/325

Abstract: Data processing apparatus comprises processing circuitry to selectively apply a vector processing operation to data items at positions within data vectors according to the states of a set of respective predicate flags associated with the positions, the data vectors having a data vector processing order, each data vector comprising a plurality of data items having a data item order, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive.

公开(公告)号：US20160026465A1

公开(公告)日：2016-01-28

申请号：US14878188

申请日：2015-10-08

Applicant: ARM Limited

Inventor： David James SEAL ,  Richard Roy GRISENTHWAITE ,  Nigel John STEPHENS

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F7/764 ,  G06F7/768 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3887

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

Abstract translation: 数据处理装置包括处理电路和指令译码器。 位
域操作指令控制处理装置，从对应的第一和第二源数据元素生成至少一个结果数据元素。 每个结果数据元素包括对应于相应的第一源数据元素的位字段的部分。 结果数据元素比插入的位域更重要的位具有基于由指令指定的控制值而被选择的前缀值作为具有零值的第一前缀值之一，具有第二前缀值的前缀值具有 相应的第二源数据元素的一部分的值，以及与第一源数据元素的位域的符号扩展对应的第三前缀值。