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公开(公告)号：US11003447B2
公开(公告)日：2021-05-11
申请号：US15743745
申请日：2016-06-23
Applicant: ARM LIMITED
Inventor： Nigel John Stephens
Abstract: A data processing system (2) supports vector processing operations performed upon vector operands comprising a plurality of vector operand elements. The data processing system includes a processor (4) having an instruction decoder (14) which decodes mixed-element-sized vector arithmetic instructions to generate control signals (16) which control processing circuitry (18) to perform arithmetic operations upon a first vector of first source operand elements ai of a first bit size A, and a second vector of second source operand elements bj of a second bit size B. The second bit size B is greater than the first bit size A.
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22.发明授权公开(公告)号：US10824350B2
公开(公告)日：2020-11-03
申请号：US16309190
申请日：2017-05-18
Applicant: ARM LIMITED
Inventor： Nigel John Stephens , Grigorios Magklis
Abstract: A data processing apparatus and method serve to manage access permission checking in respect of contingent memory access operations (the access permission failure of which does not alter program flow) in dependence of a contingent-access permission checking disable flag. If the contingent access disable flag has a first value, then this disables memory permission circuitry e.g. a walk state machine 22, from performing a check as to whether or not the memory access circuitry is permitted to perform a requested memory access. Non-contingent memory accesses are able to utilise the memory permission circuitry irrespective of the value of the contingent-access permission checking disable flag.
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公开(公告)号：US10719383B2
公开(公告)日：2020-07-21
申请号：US15743392
申请日：2016-06-21
Applicant: ARM LIMITED
Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.
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公开(公告)号：US20150186142A1
公开(公告)日：2015-07-02
申请号：US14659662
申请日：2015-03-17
Applicant: ARM Limited
Inventor： Nigel John Stephens , David James Seal
IPC: G06F9/30
CPC classification number: G06F9/30149 , G06F9/30043 , G06F9/30098 , G06F9/3016 , G06F9/30192 , G06F9/345 , G06F9/355
Abstract: A data processing system includes a processor core and a memory. The processor core includes processing circuitry controlled by control signals generated by decoder circuitry which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.
Abstract translation: 数据处理系统包括处理器核和存储器。 处理器核心包括由解码器电路产生的控制信号控制的处理电路，其解码程序指令。 程序指令包括具有第一操作数大小的第一输入操作数和第二输入操作数大小的第二输入操作数的混合操作数大小指令（加载/存储指令或算术指令），其中第二操作数大小小于第一操作数大小 操作数大小。 所执行的处理首先将第二操作数转换为具有第一操作数大小。 然后，处理使用第一操作数大小的第一操作数作为输入并且现在转换为具有第一操作数大小的第二操作数作为输入产生第三操作数。
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公开(公告)号：US11314514B2
公开(公告)日：2022-04-26
申请号：US15741303
申请日：2016-06-23
Applicant: ARM Limited
Inventor： Nigel John Stephens , Grigorios Magklis , Alejandro Martinez Vicente , Nathanael Premillieu
Abstract: A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.
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Patent Agency Ranking
公开(公告)号：US11106465B2
公开(公告)日：2021-08-31
申请号：US16650999
申请日：2018-11-15
Applicant: Arm Limited
Inventor： Mbou Eyole , Nigel John Stephens , Neil Burgess , Grigorios Magklis
Abstract: Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.
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公开(公告)号：US11074214B2
公开(公告)日：2021-07-27
申请号：US16531210
申请日：2019-08-05
Applicant: Arm Limited
Inventor： Jelena Milanovic , Lee Evan Eisen , Nigel John Stephens
Abstract: Data processing apparatus comprises processing circuitry to apply processing operations to one or more data items of a linear array comprising a plurality, n, of data items at respective positions in the linear array, the processing circuitry being configured to access an array of n×n storage locations, where n is an integer greater than one, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, as a linear array, a set of n storage locations arranged in an array direction selected, under control of the array access instruction, from a set of candidate array directions comprising at least a first array direction and a second array direction different to the first array direction.
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公开(公告)号：US11068268B2
公开(公告)日：2021-07-20
申请号：US16531208
申请日：2019-08-05
Applicant: Arm Limited
Inventor： Nigel John Stephens , David Hennah Mansell , Richard Roy Grisenthwaite , Matthew Lucien Evans
IPC: G06F9/30
Abstract: An apparatus comprises: an instruction decoder and processing circuitry. In response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder controls the processing circuitry to perform a processing operation on at least one input data structure to generate an output data structure. Each input/output data structure comprises an arrangement of data corresponding to a plurality of memory addresses. The apparatus comprises two or more sets of one or more data structure metadata registers, each set associated with a corresponding data structure identifier and designated to store address-indicating metadata for identifying the memory addresses for the data structure identified by the corresponding data structure identifier.
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公开(公告)号：US10430192B2
公开(公告)日：2019-10-01
申请号：US15748734
申请日：2016-07-28
Applicant: ARM LIMITED
Inventor： Nigel John Stephens , Grigorios Magklis , Alejandro Martinez Vicente , Nathanael Premillieu , Mbou Eyole
Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.
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公开(公告)号：US10409602B2
公开(公告)日：2019-09-10
申请号：US15741551
申请日：2016-06-21
Applicant: ARM Limited
Inventor： Nigel John Stephens
Abstract: A data processing system (2) includes processing circuitry (18) and decoder circuitry (14) for decoding program instructions and controlling the processor circuitry. The decoder circuitry is responsive to a vector operand bit size dependant instruction executed within a selected exception level state of a hierarchy of exception level states to control the processing circuitry to perform processing with a vector operand bit size governed by a limiting value of the vector operand bit size associated with the currently selected exception level state, any programmable limit value set for an exception level state closer to a top exception level state within the hierarchy and the implemented limit.
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