公开(公告)号：US20170178279A1

公开(公告)日：2017-06-22

申请号：US15369778

申请日：2016-12-05

Applicant: ARM Limited

Inventor： Sandeep Kakarlapudi ,  Marius Bjørge ,  Jan-Harald Fredriksen

IPC: G06T1/20 ,  G06T15/80 ,  G06T15/10

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T15/10 ,  G06T15/80 ,  G06T2210/52 ,  H04N13/122

Abstract: In a graphics processing system, when rendering plural views of the same scene (step 43), such as for stereoscopic rendering, the vertex shading operation is configured so that rather than executing the vertex shader program separately for each view that is being rendered, a single vertex shading program is executed once for all the views. The vertex shader program that is executed is configured to, for view-dependent operations, perform the respective operation separately for each view (step 48), so as to derive an appropriate vertex shaded output attribute value for each view, and is configured to, for vertex shading operations that are not dependent upon the view being rendered, perform those vertex shading operations only once for the set of views and to provide only a single vertex shaded output value for each vertex attribute in question for the set of views (step 49).

公开(公告)号：US12266052B2

公开(公告)日：2025-04-01

申请号：US17989548

申请日：2022-11-17

Applicant: Arm Limited

Inventor： Tord Kvestad Øygard ,  Philip Carlos Garcia ,  Sandeep Kakarlapudi

IPC: G06T15/40 ,  G06T15/00

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output.

公开(公告)号：US20240169648A1

公开(公告)日：2024-05-23

申请号：US18509441

申请日：2023-11-15

Applicant: Arm Limited

Inventor： Ole Magnus Ruud ,  Sandeep Kakarlapudi ,  Tord Kvestad Øygard ,  Per Kristian Kjøll

IPC: G06T15/00 ,  G06T11/40

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives for a tile are processed to determine visibility information, the visibility information being usable to determine whether fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.

公开(公告)号：US11972503B2

公开(公告)日：2024-04-30

申请号：US17662350

申请日：2022-05-06

Applicant: Arm Limited

Inventor： Toni Viki Brkic ,  Sandeep Kakarlapudi ,  Tord Kvestad Øygard ,  Saurav Arjun

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline that includes an early culling tester that can access plural different culling test data buffers is disclosed. Information is maintained indicating which of the plural culling test data buffers is expected to be accessed, and the information is used to control the early culling tester. The information may be used to control the early culling tester such that processing delays associated with waiting for dependencies to resolve are reduced.

公开(公告)号：US11010959B2

公开(公告)日：2021-05-18

申请号：US15497129

申请日：2017-04-25

Applicant: ARM Limited

Inventor： Sandeep Kakarlapudi ,  Andreas Engh-Halstvedt ,  Samuel Martin ,  Edvard Fielding

IPC: G06T15/20 ,  G09G5/373 ,  G06F3/01 ,  G06T1/20 ,  G06T15/00 ,  G06T15/04 ,  G06T17/05 ,  G06T17/10 ,  G06T19/20 ,  G09G5/14 ,  G06T1/60 ,  G06T11/40

Abstract: When performing foveated rendering, a graphics processor is controlled to render plural, e.g. three, different resolution versions from the same viewpoint for a scene. The rendered different resolution images are then appropriately combined (composited) to provide the output “foveated” image (output frame) that is displayed.
The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.

公开(公告)号：US10607400B2

公开(公告)日：2020-03-31

申请号：US15594969

申请日：2017-05-15

Applicant: ARM Limited

Inventor： Sandeep Kakarlapudi ,  Jorn Nystad ,  Andreas Due-Engh Halstvedt

IPC: G06T1/20 ,  G06T15/40 ,  G06T11/40 ,  H04N13/275 ,  G06T15/04 ,  G06T15/80 ,  G06T19/20 ,  G06T15/00

Abstract: A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. Vertex shading circuitry then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further, to generate, inter alia, a single vertex shaded attribute value for the set of plural views.

公开(公告)号：US20190340722A1

公开(公告)日：2019-11-07

申请号：US16402031

申请日：2019-05-02

Applicant: Arm Limited

Inventor： Arne Aas ,  Sandeep Kakarlapudi ,  Hakan Lars-Goran Persson

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/52

Abstract: When a processing resource of a data processing system is to perform processing tasks for applications executing on a host processor, the host processor prepares a plurality of command streams to cause the processing resource to perform the processing tasks. When a processing task to be added to a command stream has a dependency on a processing task or tasks that will be included in another command stream, a wait command is added to the command stream that is to include the processing task that has a dependency on a processing task or tasks that will be included in the another command stream, to cause the processing resource to delay executing subsequent commands in the command stream after the wait command, until the processing resource has reached a particular position in the another command stream.

公开(公告)号：US20170316601A1

公开(公告)日：2017-11-02

申请号：US15497129

申请日：2017-04-25

Applicant: ARM Limited

Inventor： Sandeep Kakarlapudi ,  Andreas Engh-Halstvedt ,  Samuel Martin ,  Edvard Fielding

IPC: G06T15/20 ,  G06T19/20 ,  G06T17/10 ,  G06T17/05 ,  G06T15/04 ,  G06F3/01 ,  G09G5/14 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40

CPC classification number: G06T15/205 ,  G06F3/01 ,  G06F3/011 ,  G06F3/013 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T17/05 ,  G06T17/10 ,  G06T19/20 ,  G06T2210/36 ,  G09G5/14 ,  G09G5/373 ,  G09G2310/04 ,  G09G2360/122

Abstract: When performing foveated rendering, a graphics processor is controlled to render plural, e.g. three, different resolution versions from the same viewpoint for a scene. The rendered different resolution images are then appropriately combined (composited) to provide the output “foveated” image (output frame) that is displayed.The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.

公开(公告)号：US09767595B2

公开(公告)日：2017-09-19

申请号：US13875822

申请日：2013-05-02

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Sandeep Kakarlapudi ,  Michael Stokes

IPC: G06T15/50 ,  G06T15/00

CPC classification number: G06T15/005

Abstract: A tile-based graphics processing pipeline 1 comprising a rasteriser 3, a renderer 6, a tile buffer 10, a write out stage 13 and a programmable processing stage 14. The tile buffer 10 stores multiple render targets for a deferred shading operation and the programmable processing stage 14 is operable to, under the control of graphics program instructions, read data from two or more of a set of multiple render targets for a deferred shading operation stored in the tile buffer 10, perform a deferred shading processing operation using the read data, and to write the result of the processing operation to an output render target in the tile buffer 10, or to external memory.

公开(公告)号：US20170193691A1

公开(公告)日：2017-07-06

申请号：US15393120

申请日：2016-12-28

Applicant: ARM Limited

Inventor： Frank Langtind ,  Andreas Due Engh-Halstvedt ,  Sandeep Kakarlapudi

IPC: G06T15/80 ,  G06T17/20 ,  G06T1/20

CPC classification number: G06T15/80 ,  G06F9/3879 ,  G06T1/20 ,  G06T15/005 ,  G06T17/20 ,  G09G5/363

Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.