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公开(公告)号:US20240237484A1
公开(公告)日:2024-07-11
申请号:US17997027
申请日:2021-10-29
Inventor: Xinwei Gao , Peng Li , Shuai Zhang
IPC: H10K59/80 , H10K59/122
CPC classification number: H10K59/873 , H10K59/122
Abstract: A mother board for a display panel, having a bonding region and a first panel region including a retaining region and a peripheral region, in which: a first light-emitting functional layer is located in the first panel region; a first adhesive layer surrounding the first panel region is adhered to a cover plate and a base substrate, and an orthographic projection of an edge of the first adhesive layer close to the bonding region on the base substrate defines a first pattern; the first light-emitting functional layer in the retaining region and the peripheral region are spaced by a first spacing layer, an orthographic projection of which on the base substrate partially overlaps with the first pattern and form a closed second pattern therewith. The orthographic projection of the first spacing layer on the base substrate is located within that of the first adhesive layer on the base substrate.
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公开(公告)号:US11380715B2
公开(公告)日:2022-07-05
申请号:US16493096
申请日:2019-03-21
Applicant: BOE Technology Group Co., Ltd.
Inventor: Hongwei Tian , Yanan Niu , Chunyang Wang , Dong Li , Zheng Liu , Shuai Zhang
IPC: H01L27/12
Abstract: A display substrate having a display area and a gate-on-array (GOA) area outside the display area is provided. The display substrate includes a base substrate; a light shielding layer on the base substrate; an insulating layer on a side of the light shielding layer away from the base substrate; and a GOA signal line on a side of the insulating layer away from the light shielding layer, and is connected electrically in parallel with a first part of the light shielding layer, the first part being in the GOA area. The display substrate includes a plurality of first vias extending through the insulating layer in the GOA area. The GOA signal line is electrically connected to the first part of the light shielding layer through the plurality of first vias respectively, thereby connecting the GOA signal line and the first part of the light shielding layer electrically in parallel.
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公开(公告)号:US11373429B2
公开(公告)日:2022-06-28
申请号:US16607341
申请日:2019-02-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Libin Liu , Hao Zhang , Shuai Zhang
IPC: G06V40/13 , H01L27/146
Abstract: A fingerprint recognition substrate, a fingerprint recognition apparatus, a manufacturing method thereof, a fingerprint recognition method, and a display device are provided. The fingerprint recognition substrate includes a base substrate including a plurality of pixel regions and a region between the plurality of pixel regions, a first electrode in the plurality of pixel regions, a light emitting layer at least in the plurality of pixel regions, and a second electrode at least in the plurality of pixel regions, and at least a plurality of light transmission holes penetrating the first electrode. At least one light transmission hole is in the region between the plurality of pixel regions, and the plurality of light transmission holes are configured to be optically coupled to a photosensor.
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公开(公告)号:US11177448B2
公开(公告)日:2021-11-16
申请号:US16611110
申请日:2019-01-23
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Shuai Zhang , Yueping Zuo , Libin Liu
Abstract: The present disclosure provides a flexible display device and a manufacturing method. The manufacturing method includes: forming a layer of flexible display devices on a support plate; etching the layer of flexible display devices on the support plate to expose a portion of the support plate at a cutting region, the cutting region being a predetermined region between two adjacent flexible display devices; and removing the layer of flexible display devices from the support plate after the etching process so as to obtain a plurality of flexible display devices separated from each other.
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公开(公告)号:US10748937B2
公开(公告)日:2020-08-18
申请号:US16051947
申请日:2018-08-01
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Yueping Zuo , Hongwei Tian , Shuai Zhang
IPC: H01L27/12 , H01L21/027 , H01L27/32 , H01L51/00 , G02F1/1368 , G02F1/1362 , G02F1/1333
Abstract: A substrate and a manufacturing method thereof and a display device are provided. The substrate includes: a base including a bendable region; an interlayer on the base and in the bendable region; and a signal line at a side, facing away from the base, of the interlayer. In the bendable region, an orthographic projection of the signal line on the base is within an orthographic projection of the interlayer on the base; and in the bendable region, the interlayer is provided with a groove on at least one side of a portion, corresponding to the signal line, of the interlayer.
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公开(公告)号:US10020328B2
公开(公告)日:2018-07-10
申请号:US15527792
申请日:2016-10-19
Applicant: BOE Technology Group Co., Ltd.
Inventor: Yu-Cheng Chan , Shuai Zhang , Qi Liu
IPC: H01L23/58 , H01L27/12 , H01L21/66 , H01L29/786
CPC classification number: H01L27/1296 , G02F1/1362 , G02F2001/136254 , H01L21/77 , H01L22/12 , H01L22/34 , H01L23/544 , H01L27/12 , H01L27/1222 , H01L27/124 , H01L27/1251 , H01L27/1255 , H01L29/78675
Abstract: The present disclosure provides a test element unit, an array substrate, a display panel, a display apparatus and a corresponding manufacturing method. The test element unit includes: a plurality of layers of test patterns, each layer of test pattern including at least one test block and at least one capacitor being formed between test blocks located in different layers, and, two electrodes of each of capacitors being two test blocks located in different layers, respectively, so that it can determined whether or not corresponding components and devices formed in the display region meet requirements by detecting the test patterns formed in the test region.
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公开(公告)号:US20170301741A1
公开(公告)日:2017-10-19
申请号:US15513290
申请日:2016-10-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Yucheng Chan , Shuai Zhang
IPC: H01L27/32 , H01L25/03 , H01L21/66 , H01L27/24 , G02F1/1362
CPC classification number: H01L27/3248 , G02F1/1362 , G02F2001/136254 , H01L22/30 , H01L25/03 , H01L27/2481
Abstract: The present application discloses an array substrate having a plurality of semiconductor elements and a plurality of test electrodes. Each of the plurality of semiconductor elements comprises a plurality of terminals, each of which is electrically connected to a different test electrode. At least one of the plurality of test electrodes is electrically connected to at least two different semiconductor elements.
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