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公开(公告)号：US12284903B2
公开(公告)日：2025-04-22
申请号：US17795547
申请日：2021-09-27
Inventor： Li Jia , Tao Gao , Yucheng Chan , Pinfan Wang
Abstract: Provided is a display substrate including a flexible base substrate, a first filling layer, and an encapsulation layer. The flexible base substrate includes at least one stretch display region. The stretch display region includes multiple pixel island regions spaced apart from each other, multiple hole regions, and a connection bridge region located between a pixel island region and a hole region. At least one hole region is provided with one or more first through holes penetrating the flexible base substrate. The first filling layer is located in the hole region and is filled in a first through hole. The encapsulation layer is located on a side of the first filling layer away from the flexible base substrate, and an orthographic projection of the encapsulation layer on the flexible base substrate is partially overlapped with or is not overlapped with the first filling layer.
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公开(公告)号：US12142212B2
公开(公告)日：2024-11-12
申请号：US18026637
申请日：2022-04-27
Inventor： Chengchung Yang , Yucheng Chan , Yangzhong Jing
IPC: G09G3/00 , G09G3/3233
Abstract: Provided are a pixel circuit, a drive method, and a display device. The pixel circuit includes a light-emitting element, a drive circuit, an energy storage circuit, a switch control circuit, a first initialization circuit, and a compensation control circuit. The switching control circuit controls a first voltage terminal to be connected to a second end of the energy storage circuit in a refresh frame and a first light-emitting phase and to control the first voltage terminal to be disconnected from the second end of the energy storage circuit in a first reset phase and a second reset phase under control of a switch control signal provided by the switch control terminal; a first initialization circuit writes a first initial voltage into the control terminal of the drive circuit under control of an initialization control signal in the first reset phase and the second reset phase.
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公开(公告)号：US11494019B2
公开(公告)日：2022-11-08
申请号：US17331854
申请日：2021-05-27
Inventor： Shuanzhu Li , Weixin Meng , Yucheng Chan , Xiangquan Zheng , Kewen Zeng , Jonguk Kwak
Abstract: The present disclosure relates to a method for manufacturing a touch display panel. The method includes providing a substrate film layer; forming a display functional film layer on the substrate film layer; forming an encapsulation film layer on a side of the display functional film layer away from the substrate film layer; forming a touch functional film layer on a side of the encapsulation film layer away from the display functional film layer; and after the touch functional film layer is formed, removing all film layers which include at least the substrate film layer and are located at opening areas to form through holes.
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公开(公告)号：US10243004B2
公开(公告)日：2019-03-26
申请号：US15540112
申请日：2016-11-01
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Shuai Zhang , Yucheng Chan
IPC: H01L29/786 , H01L27/12 , H01L21/02 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/49
Abstract: Disclosed are a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), a method for fabricating the same, an array substrate, a display panel, and a display device. The LTPS TFT includes an active layer, a source, a drain, a gate, and a gate insulating layer which are arranged on a substrate. The gate insulating layer is arranged between the active layer and the gate, and a graphene oxide layer which is arranged between the active layer and the gate insulating layer. Since the graphene oxide layer is arranged between the active layer and the gate insulating layer, the interface between the active layer and the gate insulating layer of polycrystalline (P-Si) has a reduced roughness and interfacial defect density, and a pre-cleaning process is not necessary for the gate insulating layer.
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公开(公告)号：US10197877B2
公开(公告)日：2019-02-05
申请号：US15504083
申请日：2016-09-09
Applicant: BOE Technology Group Co., Ltd.
Inventor： Yucheng Chan , Shuai Zhang
IPC: G02F1/13 , G02F1/1362 , H01L21/77 , H01L27/12 , G02F1/1343 , G02F1/1368
Abstract: An array substrate includes multiple pattern layers disposed in a display region and a test unit disposed in a non-display region, the test unit includes at least one of a test component and a test transistor. The test component includes a test block pattern and a test line pattern; the test block pattern is disposed in the same layer as one layer of the multiple pattern layers, the test line pattern is disposed in the same layer as one layer of the multiple pattern layers, and the test block pattern and the test line pattern are disposed in different layers; the orthographic projection of the test line pattern on the array substrate surrounds the periphery of the orthographic projection of the test block pattern on the array substrate; and the test block pattern or the test line pattern is connected to the test transistor.
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Patent Agency Ranking
公开(公告)号：US09893131B2
公开(公告)日：2018-02-13
申请号：US15513290
申请日：2016-10-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yucheng Chan , Shuai Zhang
IPC: H01L27/32 , H01L25/03 , H01L21/66 , H01L27/24 , G02F1/1362
CPC classification number: H01L27/3248 , G02F1/1362 , G02F2001/136254 , H01L22/30 , H01L25/03 , H01L27/2481
Abstract: The present application discloses an array substrate having a plurality of semiconductor elements and a plurality of test electrodes. Each of the plurality of semiconductor elements comprises a plurality of terminals, each of which is electrically connected to a different test electrode. At least one of the plurality of test electrodes is electrically connected to at least two different semiconductor elements.
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公开(公告)号：US12232349B2
公开(公告)日：2025-02-18
申请号：US17229213
申请日：2021-04-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Pinfan Wang , Chenyu Chen , Lujiang Huangfu , Fangxu Cao , Yucheng Chan
IPC: H01L51/52 , G02F1/1333 , H10K50/84 , B32B7/12
Abstract: The present disclosure relates to a display device, which includes a curved cover plate, an optical adhesive layer, and a display module that are sequentially disposed in a thickness direction thereof. The display module includes a curved surface region, the curved surface region being curved in at least two intersecting directions to form a spherical surface; the curved surface region comprises a first sub-area and a second sub-area, the second sub-area is located on a side of the first sub-area away from a center of curvature of the spherical surface; the second sub-area is wavy in the thickness direction, the wavy second sub-area is composed of a plurality of arc-shaped structures, and protruding directions of adjacent arc-shaped structures are opposite to each other; and the optical adhesive layer is completely attached to each of the arc-shaped structures.
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公开(公告)号：US11587953B2
公开(公告)日：2023-02-21
申请号：US17026503
申请日：2020-09-21
Inventor： Peng Huang , Tao Gao , Bingqiang Gui , Yucheng Chan
Abstract: A drive backplane and a display panel are provided, the drive backplane includes: a substrate; and an oxide thin film transistor arranged on the substrate, wherein the oxide thin film transistor includes: an oxide active layer; a first gate structure disposed on a side of the oxide active layer away from the substrate; and a second gate structure disposed between the oxide active layer and the substrate; wherein at least one of the first gate structure and the second gate structure comprises a plurality of gate electrodes spaced apart along a direction in which the oxide active layer extends.
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公开(公告)号：US11348356B2
公开(公告)日：2022-05-31
申请号：US16521077
申请日：2019-07-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yucheng Chan , Shuai Zhang
Abstract: The present disclosure provides a display substrate which includes: a base substrate; a light emitting layer located on the base substrate, the light emitting layer including light emitting regions and non-light emitting regions which are arranged alternately, the light emitting regions including multiple light emitting units; and the display substrate further includes a fingerprint recognition region including a touch layer which is disposed on a side of the light emitting layer distal to the base substrate and corresponds to the non-light emitting regions of the light emitting layer, the touch layer including an opaque pattern; the touch layer is provided with at least one pinhole.
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10.发明授权公开(公告)号：US11133196B2
公开(公告)日：2021-09-28
申请号：US16303959
申请日：2018-05-23
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Bin Zhang , Chienhung Liu , Yucheng Chan , Xuefei Sun , Tingting Zhou
IPC: H01L21/8234 , H01L29/66 , H01L29/786 , H01L21/324 , H01L21/02
Abstract: A gate electrode and a method for manufacturing the same, and a method for manufacturing an array substrate are provided. The method for manufacturing a gate electrode may include: providing a substrate, wherein the substrate includes a gate electrode region and a non-gate electrode region; and forming a gate electrode layer on the substrate, wherein the gate electrode layer includes a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region. According to the gate electrode and the method for manufacturing the same, and the method for manufacturing an array substrate, step difference can be eliminated, thereby avoiding an influence of the step difference on the crystallization property of a polysilicon material when an Excimer Laser Annealing (ELA) process is performed on the amorphous silicon layer, and obtaining a better crystallization effect.
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