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42 条记录 (耗时 0.033 秒)

    Phase shift mask and electronic component manufacturing method
    22.
    发明授权
    Phase shift mask and electronic component manufacturing method 有权

    公开(公告)号：US11385537B2

    公开(公告)日：2022-07-12

    申请号：US16343756

    申请日：2018-10-26

    申请人： BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

    发明人： Xiaoxiang Zhang ,  Mingxuan Liu ,  Huibin Guo ,  Yongzhi Song ,  Xiaolong Li ,  Wenqing Xu ,  Zumou Wu

    IPC分类号： G03F1/32 ,  G03F1/30 ,  G03F1/36 ,  G03F1/26 ,  H01L21/027

    摘要： A phase shift mask includes a transparent substrate and light-shielding portions. The light-shielding portions include a first light-shielding portion, and over one side of it, a first compensating light-shielding portion, which has a first distance to the first light-shielding portion and a first width smaller than a resolution of an exposing machine utilized for an exposure process using the phase shift mask. The light-shielding portions can further include a second compensating light-shielding portion, having a second distance to another side of the first light-shielding portion and a second width smaller than the resolution of the exposing machine. The first distance and the second distance respectively allow the first and the second compensating light-shielding portion to reduce an exposure at a region corresponding to two sides of the first light-shielding portion during the exposure process. A method manufacturing an electronic component utilizing the phase shift mask is also provided.

    Shift register unit and driving method, gate drive circuit, and display apparatus
    29.
    发明授权
    Shift register unit and driving method, gate drive circuit, and display apparatus 有权

    公开(公告)号：US10140911B2

    公开(公告)日：2018-11-27

    申请号：US15508608

    申请日：2016-09-22

    申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

    发明人： Xiaoxiang Zhang ,  Zheng Liu ,  Mingxuan Liu ,  Huibin Guo ,  Xi Chen

    IPC分类号： G09G3/20 ,  G11C19/28

    摘要： The present application discloses a shift register unit for outputting a gate driving signal to control image display in an operation cycle including sequentially an input phase, an output phase, an output-suspending phase, the shift register unit including a first node-control circuit connected to a pull-up node and a first pull-down node; a second node-control circuit connected to a pull-down control node and the pull-up node; a pull-up circuit connected to the pull-up node, a first input terminal for receiving a first clock signal, and an output terminal for outputting the gate driving signal, and configured to control the first clock signal to be passed from the first input terminal to the output terminal when the pull-up node is at a first potential level; a third node-control circuit connected to the pull-up node, the first pull-down node, the pull-down control node, and a second input terminal for receiving a second clock signal; and configured to control the first pull-down node to receive the second clock signal from the second input terminal when the pull-down control node is at the first potential level; a first pull-down circuit connected to the first pull-down node and the output terminal to control a second potential level to be passed to the output terminal when the first pull-down node is at the first potential level; a fourth node-control circuit connected to a second pull-down node and the pull-down control node to control the second pull-down node at the second potential level during the input phase and the output phase and to maintain an inverted potential level between the second pull-down node and the first pull-down node during the output-suspending phase; and a second pull-down circuit connected to the second pull-down node and the output terminal to yield a second potential level at the output terminal when the second pull-down node is at the first potential level, the first node-control circuit being further connected to the second pull-down node to control the pull-up node at the second potential level when the second pull-down node is at the first potential level.