公开(公告)号：US5620912A

公开(公告)日：1997-04-15

申请号：US462042

申请日：1995-06-05

申请人： Lee Y. Hwang ,  Hong S. Kim

发明人： Lee Y. Hwang ,  Hong S. Kim

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234

CPC分类号： H01L29/66636 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41766

摘要： A semiconductor device and manufacturing method wherein a gate insulating film is formed on a semiconductor substrate. A gate is formed on the gate insulating film and a sidewall spacer is formed on respective sides of the gate. The substrate is etched at the respective sides of the gate to form respective recessed parts of the substrate. An insulating film is provided on the recessed parts of the substrate and the recessed parts are filled with a semiconductor layer. Impurity regions are formed contacting the semiconductor layer in the semiconductor substrate on the respective sides of the gate.

摘要翻译： 一种半导体器件及其制造方法，其中在半导体衬底上形成栅极绝缘膜。 栅极形成在栅极绝缘膜上，并且在栅极的相应侧上形成侧壁间隔物。 衬底在栅极的相应侧被蚀刻以形成衬底的相应的凹陷部分。 在基板的凹部上设置绝缘膜，并且用半导体层填充凹部。 在半导体衬底的栅极的相应侧上与半导体层接触形成杂质区。

公开(公告)号：US5387533A

公开(公告)日：1995-02-07

申请号：US109520

申请日：1993-08-20

申请人： Hong S. Kim

发明人： Hong S. Kim

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/90 ,  H01L28/91 ,  H01L28/92

摘要： A DRAM having a dual cell plate structure and a method of making this DRAM are provided. The DRAM is made by forming two field insulation films with a constant interval on a semiconductor substrate and forming word lines uniformly spaced from each other along with the associated bit lines. The specific structure and method for this DRAM reduces the parasitic capacitance between the bit lines and the word lines so that the fabrication of the DRAM may be easily performed.

摘要翻译： 提供具有双单元板结构的DRAM和制造该DRAM的方法。 通过在半导体衬底上形成具有恒定间隔的两个场绝缘膜并且形成与相关位线相互均匀间隔开的字线来制造DRAM。 该DRAM的具体结构和方法减少了位线和字线之间的寄生电容，从而可以容易地执行DRAM的制造。

公开(公告)号：US5290726A

公开(公告)日：1994-03-01

申请号：US836690

申请日：1992-02-18

申请人： Hong S. Kim

发明人： Hong S. Kim

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L28/87 ,  H01L27/10817

摘要： A method of making dynamic random access memory cells having stacked capacitors of fin structures enabling the extension of the capacitor regions, irrespective of the used design rule. The method uses insulation layers having different etch selectivities, in order to extend the area of capacitor regions. The method comprises the steps of depositing three insulation layers on a semiconductor substrate, etching the uppermost insulation layer partially and then wet etching the intermediate insulation layer to remove its exposed portions completely and its hidden portions disposed beneath the third insulation layer partially to a predetermined length for extending the area of capacitors regions. The wet etch time of the insulation layers are controlled to control the etched length. With this extension of the area of capacitor regions, the buried contacts are formed by wet etching and are stable. Also, the number of mask processes is reduced, thereby enabling the manufacturing process to be simplified.

摘要翻译： 制造具有层叠电容器的动态随机存取存储器单元的方法，使得能够扩展电容器区域，而与所使用的设计规则无关。 该方法使用具有不同蚀刻选择性的绝缘层，以便扩展电容器区域的面积。 该方法包括以下步骤：在半导体衬底上沉积三个绝缘层，部分地蚀刻最上面的绝缘层，然后湿式蚀刻中间绝缘层以完全去除其暴露部分，并将其隐藏部分设置在第三绝缘层的下面部分到预定长度 用于扩展电容器区域的面积。 控制绝缘层的湿蚀刻时间以控制蚀刻长度。 通过电容器区域的这种扩展，埋入触点通过湿蚀刻形成并且是稳定的。 而且，掩模处理的数量减少，从而能够简化制造工艺。