公开(公告)号：US08229062B2

公开(公告)日：2012-07-24

申请号：US12868257

申请日：2010-08-25

Applicant: Hang Yip Liu ,  Sebastian Schmidt ,  Benjamin Szu-Min Lin

Inventor： Hang Yip Liu ,  Sebastian Schmidt ,  Benjamin Szu-Min Lin

IPC: G03F1/32 ,  G21K5/00

CPC classification number: G03F1/36 ,  G03F1/50 ,  G03F7/70283

Abstract: A system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a photoresist layer is effectuated in predetermined patterns through an exposure mask having light-transmissive openings in correspondence to the predetermined patterns. The exposure mask has areas densely populated with the light-transmissive openings and areas sparsely populated with the light-transmissive openings. Light is attenuated through the densely populated light-transmissive openings by a different amount than through the sparsely populated light-transmissive openings.

Abstract translation: 一种用于补偿光刻工艺中图案成像中的邻近效应的系统和方法。 通过具有对应于预定图案的透光开口的曝光掩模，以预定图案实现光致抗蚀剂层的曝光。 曝光掩模具有由透光开口和由透光开口稀疏地填充的区域密集地区域。 光通过密集居住的透光开口被衰减不同于通过疏散人口的透光开口的量。

公开(公告)号：US20070182948A1

公开(公告)日：2007-08-09

申请号：US11307448

申请日：2006-02-08

Applicant: Benjamin Szu-Min Lin ,  Sho-Shen Lee

Inventor： Benjamin Szu-Min Lin ,  Sho-Shen Lee

IPC: G03B27/32

CPC classification number: G03B27/42 ,  G03D3/00 ,  G03F7/70341 ,  G03F9/7065 ,  G03F9/7096

Abstract: A semiconductor exposure method that uses a semiconductor exposure apparatus to expose a wafer is described. The semiconductor exposure apparatus comprises at least an exposure lens, a platform for supporting the wafer and a liquid-circulating device. The liquid-circulating device supplies a liquid to the space between the wafer and the exposure lens during exposure. One major feature of the present invention is that at least one aligning light source is used to perform an alignment operation for aligning the supporting platform before the actual exposure, wherein the aligning light source has a particular wavelength in which the effect on the aligning light source due to the evaporation of the liquid is minimized to prevent the liquid from affecting the alignment operation.

Abstract translation: 描述了使用半导体曝光装置来暴露晶片的半导体曝光方法。 半导体曝光装置至少包括曝光透镜，用于支撑晶片的平台和液体循环装置。 液体循环装置在曝光期间将液体供应到晶片和曝光透镜之间的空间。 本发明的一个主要特征是使用至少一个对准光源来进行对准操作，以在实际曝光之前对准支撑平台，其中对准光源具有特定波长，其中对对准光源的影响 由于液体的蒸发被最小化以防止液体影响对准操作。

公开(公告)号：US20060257795A1

公开(公告)日：2006-11-16

申请号：US10908512

申请日：2005-05-16

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03F7/26

CPC classification number: H01L21/28123 ,  H01L21/32139

Abstract: A method for forming a composite pattern including different types of patterns is described. A substrate having a material layer thereon is provided, and two or more masks each having at least one type of pattern thereon are provided, wherein an imaginary pattern defined by the overlap between the patterns of all of the masks includes the at least one type of pattern of each mask. The following steps (1)-(3) are then performed for multiple cycles, with a different mask being used in each cycle, until all of the masks have been used. In step (1), one mask is used to form one photoresist pattern over the substrate. In step (2), the material layer is etched using the photoresist pattern as a mask. In step (3), the photoresist pattern is removed.

Abstract translation: 描述了形成包括不同类型图案的复合图案的方法。 提供其上具有材料层的衬底，并且提供两个或更多个各自具有至少一种类型的图案的掩模，其中由所有掩模的图案之间的重叠所限定的假想图案包括至少一种类型的 每个面具的图案。 然后执行以下步骤（1） - （3）多个周期，在每个周期中使用不同的掩模，直到使用所有掩模。 在步骤（1）中，使用一个掩模在衬底上形成一个光致抗蚀剂图案。 在步骤（2）中，使用光致抗蚀剂图案作为掩模蚀刻材料层。 在步骤（3）中，去除光致抗蚀剂图案。

公开(公告)号：US07052808B2

公开(公告)日：2006-05-30

申请号：US10364664

申请日：2003-02-11

Applicant: Hang Yip Liu ,  Sebastian Schmidt ,  Benjamin Szu-Min Lin

Inventor： Hang Yip Liu ,  Sebastian Schmidt ,  Benjamin Szu-Min Lin

IPC: G03F1/08

CPC classification number: G03F1/36 ,  G03F1/50 ,  G03F7/70283

Abstract: An apparatus, system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a photoresist layer is effectuated in predetermined patterns through an exposure mask having light-transmissive openings in correspondence to the predetermined patterns. The exposure mask has areas densely populated with the light-transmissive openings and areas sparsely populated with the light-transmissive openings. Light is attenuated through the densely populated light-transmissive openings by a different amount than through the sparsely populated light-transmissive openings.

Abstract translation: 一种用于补偿光刻工艺中图案成像中的邻近效应的装置，系统和方法。 通过具有对应于预定图案的透光开口的曝光掩模，以预定图案实现光致抗蚀剂层的曝光。 曝光掩模具有由透光开口和由透光开口稀疏地填充的区域密集地区域。 光通过密集居住的透光开口被衰减不同于通过疏散人口的透光开口的量。

公开(公告)号：US06849393B2

公开(公告)日：2005-02-01

申请号：US10248745

申请日：2003-02-14

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03C5/00 ,  G03F1/30 ,  G03F9/00 ,  G06F17/50

CPC classification number: G03F1/30 ,  G03F1/70

Abstract: A phase shifting lithographic process capable of creating a shrunk fine line pattern on a photoresist layer coated on a semiconductor wafer is disclosed. A first phase shift mask is prepared, which comprises thereon a first phase shift clear area, a second phase shift clear area situated adjacent to the first phase shift clear area, a vertical control chrome line section disposed at a boundary between the first phase shift clear area and the second phase shift clear area, and a horizontal opaque area connected to the vertical control chrome line section in an orthogonal manner. A first exposure process is implemented to expose the photoresist layer to light transmitted from clear areas of the first phase shift mask so as to form a vertical fine line image corresponding to the vertical control chrome line section disposed at a boundary between the first phase shift clear area and the second phase shift clear area, a horizontal unexposed area connected to the vertical fine line image in an orthogonal manner, and a peripheral unexposed line pattern. A second phase shift mask is prepared, which comprises thereon a third phase shift clear area, a fourth phase shift clear area situated adjacent to the third phase shift clear area, a horizontal control chrome line section disposed at a boundary between the third phase shift clear area and the fourth phase shift clear area, and a vertical opaque area connected to the horizontal control chrome line section in an orthogonal manner for shielding the vertical fine line image on the photoresist layer. A second exposure process is implemented to expose the photoresist layer to light transmitted from clear areas of the second phase shift mask so as to form a horizontal fine line image corresponding to the horizontal control chrome line section disposed at a boundary between the third phase shift clear area and the fourth phase shift clear area.

Abstract translation: 公开了一种能够在涂覆在半导体晶片上的光致抗蚀剂层上产生收缩细线图案的相移光刻工艺。 准备第一相移掩模，其包括第一相移清除区域，与第一相移清除区域相邻的第二相移清除区域，设置在第一相移清除区域之间的边界处的垂直控制铬线部分 区域和第二相移清除区域，以及以垂直方式连接到垂直控制铬线部分的水平不透明区域。 实施第一曝光处理以将光致抗蚀剂层暴露于从第一相移掩模的透明区域透射的光，以形成对应于设置在第一相移透明区域之间的边界处的垂直控制铬线部分的垂直细线图像 区域和第二相移清除区域，以垂直方式连接到垂直细线图像的水平未曝光区域和周边未曝光线图案。 制备第二相移掩模，其包括第三相移透明区域，与第三相移透明区域相邻设置的第四相移透明区域，设置在第三相移透明区域之间的边界处的水平控制铬线部分 区域和第四相移透明区域，以及以垂直方式连接到水平控制铬线部分的垂直不透明区域，用于屏蔽光致抗蚀剂层上的垂直细线图像。 实施第二曝光处理以将光致抗蚀剂层暴露于从第二相移掩模的透明区域透射的光，以形成对应于设置在第三相移透明区域之间的边界处的水平控制铬线部分的水平细线图像 区域和第四相位清除区域。

公开(公告)号：US06348287B1

公开(公告)日：2002-02-19

申请号：US09495247

申请日：2000-01-31

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03F900

CPC classification number: G03F1/32 ,  G03F1/28

Abstract: A multiphase phase shifting mask is described. The multiphase phase shifting mask comprises a transparent substrate; a lightly transparent material shifting an exposure light by about 180° in phase on the transparent substrate, a first group of transparent hole features shifting the exposure light by about 90° in phase on the transparent substrate, a second group of transparent hole features shifting the exposure light by about 270° in phase on the transparent substrate, and at least one transparent hole feature shifting the exposure light by about 0° in phase on the transparent substrate. The first and the second groups of transparent hole features are alternatively arranged with each other. The transparent hole feature shifting the exposure light by about 0° in phase is spaced apart from but substantially surrounded by the first and the second groups of transparent hole features. Each of the hole features shifting the exposure light by about 90° in phase, the hole features shifting the exposure light by about 270° in phase, and the hole feature shifting the exposure light by about 0° in phase is adjacently surrounded by the lightly transparent material shifting the exposure light by about 180° in phase.

Abstract translation: 描述多相移相掩模。 多相移相掩模包括透明基板; 透明材料将曝光光在相位上相移约180°，第一组透明孔将曝光光在相位上移动约90°透明基片，第二组透明孔将第 曝光光在透明基板上的相位大约为270°，并且至少一个透明孔将透光基底上的曝光光相位相移约0°。 第一组和第二组透明孔特征彼此交替布置。 透明孔的特征是将相机的曝光光移动大约0°，与第一和第二组透明孔特征基本上相隔开。 每个孔的特征是将曝光光相位移动大约90°，孔的特征是将曝光光相位移动大约270°，并且将特征将曝光光移相约0°的相位相邻地被轻微地包围 透明材料将曝光光相位移动约180°。

公开(公告)号：US06291338B1

公开(公告)日：2001-09-18

申请号：US09605089

申请日：2000-06-26

Applicant: Jhy-Jyi Sze ,  Benjamin Szu-Min Lin

Inventor： Jhy-Jyi Sze ,  Benjamin Szu-Min Lin

IPC: H01L214763

CPC classification number: H01L21/76897

Abstract: A method of fabricating a via plug for self-aligned interconnects is provided. The method features initially forming a polysilicon buffer layer and a silicon oxide layer in sequence on an inter-polysilicon dielectric (IPD) layer, followed by forming a trench opening in the silicon oxide layer. The trench opening is then filled with a metal line. A patterned photoresist layer is formed on the silicon oxide layer to form a photoresist opening which exposes a part of the metal line. The exposed part of the metal line and a part of the polysilicon buffer layer are removed to expose a part of the IPD layer, followed by removing the photoresist layer and the silicon oxide layer. With the polysilicon buffer layer and the metal line serving as a mask, the exposed part of the IPD layer is removed to form a via opening. The via opening is then filled with a polysilicon layer which is formed on the polysilicon buffer layer and the metal line. The polysilicon layer, the polysilicon buffer layer, and the metal line are etched until the IPD layer is exposed to form a via plug.

Abstract translation: 提供一种制造用于自对准互连的通孔塞的方法。 该方法首先在多晶硅间电介质（IPD）层上依次形成多晶硅缓冲层和氧化硅层，然后在氧化硅层中形成沟槽开口。 然后用金属线填充沟槽开口。 在氧化硅层上形成图案化的光致抗蚀剂层，以形成曝光金属线的一部分的光刻胶开口。 除去金属线的暴露部分和多晶硅缓冲层的一部分以露出IPD层的一部分，然后除去光致抗蚀剂层和氧化硅层。 利用多晶硅缓冲层和金属线作为掩模，去除IPD层的暴露部分以形成通孔。 然后，在多晶硅缓冲层和金属线上形成多晶硅层填充通路孔。 蚀刻多晶硅层，多晶硅缓冲层和金属线直到IPD层暴露以形成通孔塞。

公开(公告)号：US06238825B1

公开(公告)日：2001-05-29

申请号：US09442839

申请日：1999-11-18

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03F900

CPC classification number: G03F1/26 ,  G03F1/30 ,  G03F1/36

Abstract: A low duty ratio mask has a plurality of masked layout patterns and a plurality of alternating scattering bars placed next to edges of each masked layout pattern. A phase shift of 180° exists between the alternating scattering bars and the corresponding masked layout pattern.

Abstract translation: 低占空比掩模具有多个掩模布局图案和放置在每个掩蔽布局图案的边缘旁边的多个交替散射条。 在交替散射条和相应的屏蔽布局图案之间存在180°的相移。

公开(公告)号：US6117757A

公开(公告)日：2000-09-12

申请号：US164966

申请日：1998-10-01

Applicant: Chuan-Fu Wang ,  Benjamin Szu-Min Lin

Inventor： Chuan-Fu Wang ,  Benjamin Szu-Min Lin

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: A method of forming landing pads for a bit line and a node contact is provided. First, a first dielectric layer is formed on a substrate having a transistor structure thereon. The first dielectric layer is defined and etched in a self-aligned process to form a contact opening to the substrate. A second dielectric layer is formed on the first dielectric layer and is etched back to form a spacer on the opening sidewall. Then, a conductive layer is formed on the first dielectric layer and fills the opening. A bit line is formed by partially removing the conductive layer through a photo-resist mask provided on the conductive layer, wherein the conductive layer filling the opening is left to form a landing pad.

Abstract translation: 提供了一种形成位线和节点接​​触的着陆焊盘的方法。 首先，在其上具有晶体管结构的基板上形成第一电介质层。 在自对准工艺中限定和蚀刻第一电介质层以形成与衬底的接触开口。 在第一电介质层上形成第二电介质层并将其回蚀刻以在开口侧壁上形成间隔物。 然后，在第一电介质层上形成导电层并填充开口。 通过通过设置在导电层上的光致抗蚀剂掩模部分去除导电层而形成位线，其中填充开口的导电层留下以形成着陆焊盘。

公开(公告)号：US6071653A

公开(公告)日：2000-06-06

申请号：US186130

申请日：1998-11-04

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03F1/00 ,  G03F1/46 ,  G03F7/00 ,  G03F9/00

CPC classification number: G03F1/46 ,  B82Y10/00 ,  G03F1/50

Abstract: A method for fabricating a photomask includes forming an anti-reflection layer on a transparent substrate. A transparent layer is formed on the anti-reflection layer. Patterning the transparent layer forms a transparent bar layer so that a portion of the ant-reflection layer is exposed. An opaque layer is formed over the substrate. A polishing process is performed to polish the opaque layer and the transparent bar layer so that a top portion of the transparent bar layer is polished and exposed. An etching back process is performed to remove a portion of the opaque layer so that the anti-reflection layer is exposed and the remains of the opaque layer forms a spacer with uniform thickness on each side of the transparent bar layer. The transparent bar layer is removed by etching so as to form the photomask.

Abstract translation: 一种制造光掩模的方法包括在透明基板上形成抗反射层。 在防反射层上形成透明层。 对透明层进行图案化形成透明的棒层，使得抗反射层的一部分露出。 在衬底上形成不透明层。 进行抛光处理以抛光不透明层和透明条层，使得透明条层的顶部被抛光和曝光。 执行蚀刻反应处理以去除不透明层的一部分，使得防反射层被曝光，并且不透明层的残余物在透明条层的每一侧上形成具有均匀厚度的间隔物。 通过蚀刻去除透明棒层以形成光掩模。