公开(公告)号：US08413401B2

公开(公告)日：2013-04-09

申请号：US13189748

申请日：2011-07-25

Applicant: Chuan-Fu Wang

Inventor： Chuan-Fu Wang

IPC: E04C2/38

CPC classification number: A47K3/34 ,  A47K2003/307

Abstract: A modular door case for bathing enclosure includes two jambs, two frame members, and four fasten components. Each frame member has an accommodating portion at ends thereof, and at least one pair clasp holes respectively formed on upper and lower walls of the accommodating portion. Each fasten component has a base, at least one pair of clasp members, and at least one compelling bolt. A clasp protrusion is disposed at opposite distal end of each clasp member, so that space between the pair of clasp members, in normal state, shrinks from the joint ends to the distal ones. Each clasp protrusion of the clasp member contacts each clasp hole of the frame member, while the base inserts into each accommodating portion. The compelling bolt is between the pair of the clasp members, and further capable of moving towards the distal ends of the clasp members.

Abstract translation: 浴室的模块化门壳包括两个边框，两个框架构件和四个紧固件。 每个框架构件在其端部具有容纳部分，并且分别形成在容纳部分的上壁和下壁上的至少一对扣环孔。 每个固定部件具有基部，至少一对扣环构件和至少一个引人注目的螺栓。 在每个扣环构件的相对的远端设置有扣环突起，使得一对扣环构件在正常状态下的空间从接合端收缩到远端。 钩扣构件的每个扣环突起接触框架构件的每个扣环孔，同时基座插入每个容纳部分。 引人注目的螺栓在一对扣环构件之间，并且还能够朝向扣环构件的远端移动。

公开(公告)号：US07465640B2

公开(公告)日：2008-12-16

申请号：US11122655

申请日：2005-05-04

Applicant: Yung-Chang Lin ,  Chia-Wen Liang ,  Chuan-Fu Wang

Inventor： Yung-Chang Lin ,  Chia-Wen Liang ,  Chuan-Fu Wang

IPC: H01L21/20

CPC classification number: H01L27/10832 ,  H01L27/10867 ,  H01L29/66181

Abstract: A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

公开(公告)号：US20060208306A1

公开(公告)日：2006-09-21

申请号：US10907006

申请日：2005-03-16

Applicant: Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

Inventor： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

IPC: H01L29/788

CPC classification number: G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

Abstract: The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

Abstract translation: 单多晶硅EEPROM包括串联连接到第二PMOS晶体管的第一PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括浮置栅极，第一P + +掺杂漏极区域和第一P + +掺杂源极区域。 第二PMOS晶体管包括栅极和第二P + +掺杂源极区域。 第一PMOS晶体管的第一P + SUP掺杂漏区用作第二PMOS晶体管的漏极。 二极管位于包括P阱和N + +掺杂区的P型衬底中。 浮栅与N阱重叠并延伸到N + +掺杂区。 浮置栅极下面的P阱和N + + / / P>掺杂区域结的重叠区域用作第一PMOS晶体管附近的雪崩注入点。

公开(公告)号：US20050202628A1

公开(公告)日：2005-09-15

申请号：US11122655

申请日：2005-05-04

Applicant: Yung-Chang Lin ,  Chia-Wen Liang ,  Chuan-Fu Wang

Inventor： Yung-Chang Lin ,  Chia-Wen Liang ,  Chuan-Fu Wang

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10832 ,  H01L27/10867 ,  H01L29/66181

Abstract: A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

公开(公告)号：US06297123B1

公开(公告)日：2001-10-02

申请号：US09725026

申请日：2000-11-29

Applicant: Jhy-Jyi Sze ,  Chuan-Fu Wang

Inventor： Jhy-Jyi Sze ,  Chuan-Fu Wang

IPC: H01L2120

CPC classification number: H01L28/84 ,  H01L21/31155 ,  H01L21/3144

Abstract: A silicon oxide layer is formed on a substrate surface of a semiconductor wafer. A node contact is formed in the silicon oxide layer. A storage node is formed on the silicon oxide layer and connects to the node contact. An ion implantation process is performed as a surface process on the silicon oxide layer. A silicon nitride layer is subsequently formed on the surfaces of the silicon oxide layer and the storage node. Finally, a high-temperature oxidation process is performed. The surface process reduces the difference in the incubation time for the silicon nitride layer deposited on the silicon oxide layer and on the surface of the storage node. The surface process also relieves problems associated with the nonuniformity in thickness of the silicon nitride layer. Neck-oxidation at the interface of the storage node and the node contact is thus prevented.

Abstract translation: 在半导体晶片的衬底表面上形成氧化硅层。 在氧化硅层中形成节点接触。 存储节点形成在氧化硅层上并连接到节点接触。 进行离子注入工艺作为氧化硅层上的表面工艺。 随后在氧化硅层和存储节点的表面上形成氮化硅层。 最后，进行高温氧化处理。 表面处理减少沉积在氧化硅层上和存储节点表面上的氮化硅层的孵育时间的差异。 表面处理也减轻了与氮化硅层厚度不均匀有关的问题。 因此防止在存储节点和节点接触的界面处的颈部氧化。

公开(公告)号：US06211021B1

公开(公告)日：2001-04-03

申请号：US09360754

申请日：1999-07-26

Applicant: Chuan-Fu Wang ,  Horng-Nan Chern

Inventor： Chuan-Fu Wang ,  Horng-Nan Chern

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/76237 ,  H01L21/823481

Abstract: A method of forming a borderless contact is described. An ion implantation process and a thermal process are performed on a device isolation structure to form a silicon nitride layer therein. During a process of forming a borderless contact window, the silicon nitride layer can serve as an etching stop layer to protect the device isolation structure from overetching. As a result, no recess is formed, and leakage current is avoided.

Abstract translation: 描述形成无边界接触的方法。 在器件隔离结构上进行离子注入工艺和热处理，以在其中形成氮化硅层。 在形成无边界接触窗的过程中，氮化硅层可以用作蚀刻停止层，以保护器件隔离结构不被过蚀刻。 结果，没有形成凹陷，并且避免了泄漏电流。

公开(公告)号：US06204117B1

公开(公告)日：2001-03-20

申请号：US09352471

申请日：1999-07-14

Applicant: Jung-Chao Chiou ,  Chuan-Fu Wang

Inventor： Jung-Chao Chiou ,  Chuan-Fu Wang

IPC: H01L218242

CPC classification number: H01L28/84 ,  H01L21/31111 ,  H01L27/10852

Abstract: A method of forming a capacitor for a dynamic random access memory (DRAM) cell using a selective hemispherical grain (s-HSG) structure after the removal of SiON by phosphoric acid (H3PO4) is disclosed. The method includes: Providing a semiconductor substrate having a semiconductor structure formed thereon; forming an interlayer dielectric layer over the semiconductor structure; patterning the interlayer dielectric layer; depositing an amorphous-silicon (a-Si) layer over the interlayer dielectric layer; depositing a SiON layer on the a-Si layer; patterning the SiON layer and the a-Si layer layer; removing the SiON layer by H3PO4 wet etching; forming a s-HSG silicon layer over the patterned a-Si layer; depositing a conformal interpoly dielectric layer along a surface of the resulting structure; and finally forming a polysilicon layer over the interpoly dielectric layer.

Abstract translation: 公开了在通过磷酸（H 3 PO 4）除去SiON之后，使用选择性半球形颗粒（s-HSG）结构形成用于动态随机存取存储器（DRAM）单元的电容器的方法。 该方法包括：提供其上形成有半导体结构的半导体衬底; 在所述半导体结构上形成层间电介质层; 图案化层间电介质层; 在所述层间电介质层上沉积非晶硅（a-Si）层; 在a-Si层上沉积SiON层; 图案化SiON层和a-Si层层; 通过H3PO4湿蚀刻去除SiON层; 在图案化的a-Si层上形成s-HSG硅层; 沿着所得结构的表面沉积共形互穿电介质层; 并最终在多晶硅电介质层上形成多晶硅层。

公开(公告)号：US6117757A

公开(公告)日：2000-09-12

申请号：US164966

申请日：1998-10-01

Applicant: Chuan-Fu Wang ,  Benjamin Szu-Min Lin

Inventor： Chuan-Fu Wang ,  Benjamin Szu-Min Lin

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: A method of forming landing pads for a bit line and a node contact is provided. First, a first dielectric layer is formed on a substrate having a transistor structure thereon. The first dielectric layer is defined and etched in a self-aligned process to form a contact opening to the substrate. A second dielectric layer is formed on the first dielectric layer and is etched back to form a spacer on the opening sidewall. Then, a conductive layer is formed on the first dielectric layer and fills the opening. A bit line is formed by partially removing the conductive layer through a photo-resist mask provided on the conductive layer, wherein the conductive layer filling the opening is left to form a landing pad.

Abstract translation: 提供了一种形成位线和节点接​​触的着陆焊盘的方法。 首先，在其上具有晶体管结构的基板上形成第一电介质层。 在自对准工艺中限定和蚀刻第一电介质层以形成与衬底的接触开口。 在第一电介质层上形成第二电介质层并将其回蚀刻以在开口侧壁上形成间隔物。 然后，在第一电介质层上形成导电层并填充开口。 通过通过设置在导电层上的光致抗蚀剂掩模部分去除导电层而形成位线，其中填充开口的导电层留下以形成着陆焊盘。

公开(公告)号：US6087216A

公开(公告)日：2000-07-11

申请号：US195760

申请日：1998-11-18

Applicant: Chuan-Fu Wang

Inventor： Chuan-Fu Wang

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10814 ,  H01L27/10852

Abstract: A method of manufacturing a DRAM capacitor utilizes spacers to form a self-aligned node contact, and thus is able to reduce the cross-sectional dimensions of the node contact. Moreover, the spacers are capable of protecting any portion of a bit line that may be exposed due to misalignment when contact opening is formed. Hence, short-circuiting of the device can be prevented. Furthermore, by shaping the lower electrode of the capacitor into a fork-shaped structure with four prongs, the surface area for capacitor coupling is increased, thus increasing the capacitance of the capacitor, as well.

Abstract translation: 制造DRAM电容器的方法利用间隔物形成自对准节点接触，因此能够减小节点接触的横截面尺寸。 此外，当形成接触开口时，间隔件能够保护由于未对准而可能暴露的位线的任何部分。 因此，可以防止装置短路。 此外，通过将电容器的下电极成形为具有四个插脚的叉状结构，电容器耦合的表面积也增加，从而增加了电容器的电容。

公开(公告)号：US6080621A

公开(公告)日：2000-06-27

申请号：US165253

申请日：1998-10-01

Applicant: Chuan-Fu Wang ,  J. S. Jason Jenq

Inventor： Chuan-Fu Wang ,  J. S. Jason Jenq

IPC: H01L21/8242 ,  H01L21/8234 ,  H01L21/8249

CPC classification number: H01L27/10852

Abstract: A method of forming a DRAM capacitor that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in a DRAM can be formed in two self-aligned contact processing operations. The capacitor of the DRAM is fabricated by forming contact node and openings within an insulating layer above a substrate, and then forming a first conductive layer conformal to the surface profile of the substrate above the substrate structure. Next, spacers are formed on the sidewalls of the conductive layer, and then a second conductive layer is formed filling the spacer between the spacers and over the substrate structure. Thereafter, a portion of the first conductive layer and the second conductive layer is removed to expose the spacers and the insulating layer. Finally, the spacers and the insulating layer are removed to expose a lower electrode structure that comprises the first and the second conductive layers.

Abstract translation: 一种形成DRAM电容器的方法，该DRAM电容器利用盖层和隔离物围绕栅极和位线，使得可以在两个自对准的接触处理操作中形成DRAM中必需的接触开口。 通过在衬底上方的绝缘层内形成接触节点和开口，然后形成与衬底结构上方的衬底的表面轮廓一致的第一导电层来制造DRAM的电容器。 接下来，在导电层的侧壁上形成间隔物，然后形成第二导电层，填充间隔物之间​​的间隔物和衬底结构上。 此后，去除第一导电层和第二导电层的一部分以露出间隔物和绝缘层。 最后，去除间隔物和绝缘层以暴露包括第一和第二导电层的下电极结构。