公开(公告)号：US07807342B2

公开(公告)日：2010-10-05

申请号：US11303301

申请日：2005-12-16

Applicant: Hang Yip Liu ,  Sebastian Schmidt ,  Benjamin Szu-Min Lin

Inventor： Hang Yip Liu ,  Sebastian Schmidt ,  Benjamin Szu-Min Lin

IPC: G03F7/20 ,  G03F1/08

CPC classification number: G03F1/36 ,  G03F1/50 ,  G03F7/70283

Abstract: An apparatus, system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a photoresist layer is effectuated in predetermined patterns through an exposure mask having light-transmissive openings in correspondence to the predetermined patterns. The exposure mask has areas densely populated with the light-transmissive openings and areas sparsely populated with the light-transmissive openings. Light is attenuated through the densely populated light-transmissive openings by a different amount than through the sparsely populated light-transmissive openings.

Abstract translation: 一种用于补偿光刻工艺中图案成像中的邻近效应的装置，系统和方法。 通过具有对应于预定图案的透光开口的曝光掩模，以预定图案实现光致抗蚀剂层的曝光。 曝光掩模具有由透光开口和由透光开口稀疏地填充的区域密集地区域。 光通过密集居住的透光开口被衰减不同于通过疏散人口的透光开口的量。

公开(公告)号：US07268070B2

公开(公告)日：2007-09-11

申请号：US10445047

申请日：2003-05-27

Applicant: Hui-Ling Huang ,  Benjamin Szu-Min Lin ,  Cheng-Chung Chen ,  George Liu

Inventor： Hui-Ling Huang ,  Benjamin Szu-Min Lin ,  Cheng-Chung Chen ,  George Liu

IPC: H01L21/47 ,  H01L21/4757

CPC classification number: G03F7/40

Abstract: There is a grain phenomenon issue of rough sidewall for patterning. Thus, imprecise grain profiles would be observed. As the critical dimensions of integrated circuit microelectronics fabrication device have decreased, the effect of grain phenomenon have become more pronounced. A profile improvement method with a thermal-compressive material and a thermal-compressive process is provided to solve the grain phenomenon issue for baseline of 0.09 um generation and beyond. With this material, the profile can be improved no matter in top view or lateral view. Furthermore, there are 0.1 um IDOF improvement and better physical etching performance.

Abstract translation: 图案粗糙的侧壁存在颗粒现象问题。 因此，将观察到不精确的颗粒轮廓。 随着集成电路微电子制造装置的关键尺寸降低，晶粒现象的影响变得更加明显。 提供了一种具有热压缩材料和热压缩工艺的轮廓改进方法，以解决0.09 um以上的基线的纹理现象问题。 使用这种材料，无论在俯视图或侧视图中，轮廓都可以改进。 此外，具有0.1um的IDOF改进和更好的物理蚀刻性能。

公开(公告)号：US20060194142A1

公开(公告)日：2006-08-31

申请号：US10906582

申请日：2005-02-25

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03C1/76

CPC classification number: G03F7/70341 ,  G03F7/2041

Abstract: A novel immersion medium for immersion lithography is provided. The immersion medium is introduced to fill a gap in between a front surface of a projection lens of a stepper and a top surface of a photoresist layer coated on a substrate positioned on a wafer stage. The present invention is characterized in that the immersion medium has a pH value matching that of the photoresist layer in order to prevent effects caused by photo acid generator (PAG) leaching from the photoresist layer to the immersion medium during exposure.

Abstract translation: 提供了一种浸没式光刻浸渍介质。 引入浸渍介质以填充步进器的投影透镜的前表面和涂覆在位于晶片台上的基板上的光致抗蚀剂层的顶表面之间的间隙。 本发明的特征在于，浸渍介质的pH值与光致抗蚀剂层的pH值相匹配，以防止在曝光期间光致酸层从浸渍介质浸出的光酸产生剂（PAG）引起的影响。

公开(公告)号：US20060191863A1

公开(公告)日：2006-08-31

申请号：US11067283

申请日：2005-02-25

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: C23F1/00

CPC classification number: H01L21/0337 ,  H01L21/0338

Abstract: A method for fabricating a mask is provided. A patterned sacrificial layer is formed over a mask material layer, and the patterned sacrificial layer has an etch selectivity different from that of the mask material layer. An isotropic etch process is performed to the mask material layer by using the patterned sacrificial layer as an etch mask to form a mask layer, wherein the dimension of the mask layer is smaller than that of the patterned sacrificial layer.

Abstract translation: 提供了一种制造掩模的方法。 图案化的牺牲层形成在掩模材料层之上，并且图案化的牺牲层具有与掩模材料层的蚀刻选择性不同的蚀刻选择性。 通过使用图案化的牺牲层作为蚀刻掩模来对掩模材料层进行各向同性蚀刻处理，以形成掩模层，其中掩模层的尺寸小于图案化牺牲层的尺寸。

公开(公告)号：US20050196951A1

公开(公告)日：2005-09-08

申请号：US10708502

申请日：2004-03-08

Applicant: Benjamin Szu-Min Lin ,  Shou-Wan Huang

Inventor： Benjamin Szu-Min Lin ,  Shou-Wan Huang

IPC: H01L21/311 ,  H01L21/4763 ,  H01L21/76

CPC classification number: H01L21/31144 ,  H01L21/76808 ,  H01L21/76844 ,  H01L21/76846

Abstract: A method of forming at least one wire on a substrate comprising at least one conductive region is provided. AnAn insulatingayer is disposed on the substrate. The method includes forming a hard mask layer on the insulating layer followed by forming at least one recess by removing portions of the hard mask layer and the insulating layer, forming a light blocking layer on the hard mask layer and the recess, and the light blocking layer and the hard mask layer forming a composite layer, forming a gap filling layer filling up the recess on the light blocking layer, forming a photoresist layer on the gap filling layer, aligning a photo mask with the recess by utilizing the composite layer as a mask, and performing an exposure/development process to form at least one pattern above the recess in the photoresist layer.

Abstract translation: 提供了一种在包括至少一个导电区域的基板上形成至少一根导线的方法。 AnAn绝缘层设置在基板上。 该方法包括在绝缘层上形成硬掩模层，然后通过去除硬掩模层和绝缘层的部分形成至少一个凹部，在硬掩模层和凹部上形成遮光层，并且阻光 层和硬掩模层形成复合层，形成填充光阻挡层上的凹部的间隙填充层，在间隙填充层上形成光致抗蚀剂层，通过利用复合层作为光掩模与凹槽对准光掩模 掩模，并且进行曝光/显影处理以在光致抗蚀剂层中的凹部之上形成至少一个图案。

公开(公告)号：US20050074678A1

公开(公告)日：2005-04-07

申请号：US10904795

申请日：2004-11-30

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03C5/00 ,  G03F1/30 ,  G03F9/00 ,  G06F17/50

CPC classification number: G03F1/30 ,  G03F1/70

Abstract: A dual phase shifting mask (PSM)/double exposure lithographic process for manufacturing a shrunk semiconductor device. A semiconductor wafer having a photoresist layer coated thereon is provided. A first phase shift mask is disposed over the semiconductor wafer and implementing a first exposure process to expose the photoresist layer to light transmitted through the first phase shift mask so as to form a latent pattern comprising a peripheral unexposed line pattern in the photoresist layer. The first phase shift mask is then replaced with a second phase shift mask and implementing a second exposure process to expose the photoresist layer to light transmitted through the second phase shift mask so as to remove the peripheral unexposed line pattern.

Abstract translation: 用于制造缩小半导体器件的双相移掩模（PSM）/双曝光光刻工艺。 提供其上涂覆有光致抗蚀剂层的半导体晶片。 第一相移掩模设置在半导体晶片上方，并且实施第一曝光工艺以将光致抗蚀剂层暴露于透过第一相移掩模的光，从而在光致抗蚀剂层中形成包括外围未曝光线图案的潜像。 然后用第二相移掩模替换第一相移掩模，并实施第二曝光处理以将光致抗蚀剂层暴露于通过第二相移掩模传输的光，以便除去周围的未曝光线图案。

公开(公告)号：US06740473B1

公开(公告)日：2004-05-25

申请号：US10065914

申请日：2002-11-28

Applicant: Benjamin Szu-Min Lin ,  Hui-Ling Huang

Inventor： Benjamin Szu-Min Lin ,  Hui-Ling Huang

IPC: G03F700

CPC classification number: G03F7/40

Abstract: A method for shrinking critical dimension of semiconductor devices includes forming a first pattern of a photoresist layer on a semiconductor device layer, by performing a blanket exposing process to expose the photoresist layer and the exposed semiconductor device layer to light having a wavelength that can be absorbed by the photoresist layer to provide the photoresist layer with a predetermined energy per unit area, thereby producing photo generated acids therein. A first thermal process is performed to diffuse the photo-generated acids formed within the photoresist layer and to equalize glass transition temperature (Tg) of the photoresist layer. A second thermal process is thereafter carried out. The first thermal process is carried out under a temperature lower than Tg of the photoresist layer.

Abstract translation: 缩小半导体器件的临界尺寸的方法包括：在半导体器件层上形成光致抗蚀剂层的第一图案，通过进行橡皮布曝光工艺，将光致抗蚀剂层和暴露的半导体器件层暴露于具有可被吸收的波长的光 通过光致抗蚀剂层提供每单位面积预定能量的光致抗蚀剂层，从而在其中产生光生酸。 执行第一热处理以扩散在光致抗蚀剂层内形成的光生酸，并平衡光致抗蚀剂层的玻璃化转变温度（Tg）。 此后进行第二热处理。 第一热处理在低于光致抗蚀剂层的Tg的温度下进行。

公开(公告)号：US06296991B1

公开(公告)日：2001-10-02

申请号：US09471078

申请日：1999-12-22

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03F900

CPC classification number: G03F1/30 ,  G03F1/34 ,  G03F7/70333 ,  G03F7/70466

Abstract: A bi-focus exposure process for exposing a wafer through a mask is described. The mask comprises a plurality of first transparent hole features having a phase shift of about 0 degrees and a plurality of second transparent hole features having a phase shift of about 180 degrees, the first and the second hole features are alternatively located on a transparent substrate, and each of the hole features is substantially and adjacently surrounded by a lightly transparent material having a phase shift of about 90 degrees on the transparent substrate. The patterns of the first hole features are printed on the wafer by exposing the wafer through the mask at a first defocus smaller than 0 &mgr;m defocus. The patterns of the second hole features are printed on the wafer by exposing the wafer through the mask at a second defocus smaller than 0 &mgr;m defocus.

Abstract translation: 描述了通过掩模使晶片曝光的双焦点曝光工艺。 掩模包括具有约0度的相移的多个第一透明孔特征和具有大约180度的相移的多个第二透明孔特征，第一和第二孔特征交替地位于透明基底上， 并且每个孔特征基本上和相邻地被在透明基底上具有大约90度的相移的轻透明材料包围。 通过在小于0um散焦的第一散焦处将晶片暴露于掩模中，将第一孔特征的图案印刷在晶片上。 通过在小于0um散焦的第二散焦处将晶片暴露于掩模中，将第二孔特征的图案印刷在晶片上。

公开(公告)号：US06296987B1

公开(公告)日：2001-10-02

申请号：US09421309

申请日：1999-10-20

Applicant: Benjamin Szu-Min Lin ,  Chien-Li Kuo

Inventor： Benjamin Szu-Min Lin ,  Chien-Li Kuo

IPC: G03F900

CPC classification number: G03F7/70466 ,  G03F1/30 ,  G03F7/0035

Abstract: A method for forming different patterns using one phase shifting mask. The phase shifting mask has a bit line contact pattern and a node contact pattern thereon. The exposure pattern is changed by using different defocus conditions. In a first defocus situation, the bit line contact pattern and the node contact pattern of the PSM are simultaneously transferred to a photoresist layer. However, in a second defocus situation, only the bit line contact pattern is transferred to the photoresist layer. A phase shifting mask thus can be used in two different photolithography processes.

Abstract translation: 一种使用一个相移掩模形成不同图案的方法。 相移掩模具有位线接触图案和其上的节点接触图案。 通过使用不同的散焦条件改变曝光图案。 在第一散焦情况下，PSM的位线接触图案和节点接触图案被同时传送到光致抗蚀剂层。 然而，在第二散焦情况下，仅将位线接触图案转移到光致抗蚀剂层。 因此，相移掩模可用于两种不同的光刻工艺。

公开(公告)号：US6124162A

公开(公告)日：2000-09-26

申请号：US207171

申请日：1998-12-07

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8234

CPC classification number: H01L28/92 ,  H01L27/10852

Abstract: A method for forming the cylindrical lower electrode of a capacitor includes the steps of providing a semiconductor substrate, and then forming an insulation layer over the substrate. Next, a contact opening is formed in the insulation layer, and then a conductive layer is formed, filling the contact opening and covering the insulation layer. Subsequently, a patterned photoresist layer is formed over the conductive layer. Thereafter, silylated photoresist spacers are formed on the sidewalls of the photoresist layer. Finally, using the spacers as a mask, the photoresist layer and a portion of the conductive layer are etched away to form the cylindrical-shaped lower electrode of a capacitor.

Abstract translation: 一种用于形成电容器的圆柱形下电极的方法包括以下步骤：提供半导体衬底，然后在衬底上形成绝缘层。 接下来，在绝缘层中形成接触开口，然后形成导电层，填充接触开口并覆盖绝缘层。 随后，在导电层上形成图案化的光致抗蚀剂层。 此后，在光致抗蚀剂层的侧壁上形成甲硅烷基化的光致抗蚀剂间隔物。 最后，使用间隔物作为掩模，蚀刻掉光致抗蚀剂层和导电层的一部分，以形成电容器的圆柱形下电极。