公开(公告)号：US10217427B2

公开(公告)日：2019-02-26

申请号：US15513952

申请日：2016-02-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yuanbo Zhang ,  Seungwoo Han ,  Xing Yao

IPC: G09G3/36

Abstract: The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal.

公开(公告)号：US20180197455A1

公开(公告)日：2018-07-12

申请号：US15682740

申请日：2017-08-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Guangliang Shang ,  Han-Seung- Woo ,  Xing Yao ,  Zhihe Jin ,  Haoliang Zheng ,  Lijun Yuan ,  Zhichong Wang

IPC: G09G3/20

Abstract: The embodiments of the present disclosure provide a partition-based gate driving method and apparatus and a gate driving unit, and relates to the field of display technology. In the embodiments of the present disclosure, the partition-based gate driving method comprises: generating a control signal according to an acquired human eye observation partition; generating a second clock signal or a third clock signal according to the control signal; and controlling a second output signal according to the second clock signal or controlling a third output signal according to the third clock signal, thereby controlling the display area to be displayed by partitions.

公开(公告)号：US09805683B2

公开(公告)日：2017-10-31

申请号：US14906475

申请日：2015-08-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xing Yao ,  Seungwoo Han ,  Yuanbo Zhang

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3677 ,  G09G3/20 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/021

Abstract: The present invention discloses a Gate-driver-On-Array (GOA) circuit and the driving method thereof and a display device. The GOA circuit comprises a driving module, a low-resolution module and at least two high-resolution modules, the driving module being connected with the low-resolution module and the at least two high-resolution modules respectively; wherein, the driving module is used to output control signal to the low-resolution module and the high-resolution modules; the low-resolution module is used to output a low-resolution signal to at least two rows of pixels under the control of the control signal during low-resolution display; and each high-resolution module is used to output a high-resolution signal to corresponding one row of pixels under the control of the control signal during high-resolution display. The GOA circuit of the present invention may be used to drive multiple rows of pixels and implement the switching between low resolution display and high resolution display.

公开(公告)号：US12230216B2

公开(公告)日：2025-02-18

申请号：US18245534

申请日：2022-05-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Zhenzhen Shan ,  Jianchao Zhu ,  Guangliang Shang ,  Xing Yao

IPC: G09G3/32 ,  G09G3/3266

Abstract: A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit configured to receive a start signal or an output signal from a previous scan unit, a first processing subcircuit, a second processing subcircuit, and an output subcircuit. The output subcircuit includes a first output transistor. The input subcircuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node. The first node is coupled to a gate electrode of the first output transistor. The first processing subcircuit includes a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal. The first reference terminal is configured to receive a first reference signal.

公开(公告)号：US11862098B2

公开(公告)日：2024-01-02

申请号：US17628779

申请日：2021-04-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Jie Zhang ,  Shuo Huang ,  Libin Liu ,  Shiming Shi ,  Hao Liu ,  Haoliang Zheng ,  Xing Yao

IPC: G09G3/3266 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G09G3/3677 ,  G11C19/28 ,  G09G2300/0852 ,  G09G2310/0286

Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.

公开(公告)号：US20210335210A1

公开(公告)日：2021-10-28

申请号：US16485994

申请日：2018-09-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng

IPC: G09G3/32

Abstract: The present application discloses a gate driver on array (GOA) circuit of a display panel. The GOA circuit includes a first GOA unit comprising a unit-circuitry structure having a pull-up node commonly coupled to three output transistors to control outputting of a first set of three gate-driving signals respectively to a first set of three gate lines associated with the display panel. The GOA circuit additionally includes a second GOA unit comprising a substantially same unit-circuitry structure cascaded with the first GOA unit and configured to control outputting a second set of three gate-driving signals respectively to a second set of three gate lines associated with the display panel. Moreover, the GOA circuit includes a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit.

公开(公告)号：US20200258463A1

公开(公告)日：2020-08-13

申请号：US15768309

申请日：2017-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seungwoo Han ,  Guangliang Shang ,  Haoliang Zheng ,  Xing Yao ,  Zhichong Wang ,  Mingfu Han ,  Lijun Yuan ,  Yunsik IM ,  Jing Lv ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28

Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

公开(公告)号：US10504469B2

公开(公告)日：2019-12-10

申请号：US15768948

申请日：2017-10-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seung Woo Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng ,  Mingfu Han ,  Zhichong Wang ,  Lijun Yuan ,  Yun Sik Im ,  Jing Lv ,  Yinglong Huang ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/3266 ,  G09G3/20 ,  G11C19/18

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

公开(公告)号：US10475409B2

公开(公告)日：2019-11-12

申请号：US15796463

申请日：2017-10-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Xing Yao ,  Guangliang Shang ,  Haoliang Zheng ,  Seung-Woo Han ,  Jiha Kim ,  Lijun Yuan ,  Zhichong Wang

IPC: G11C19/00 ,  G09G3/36 ,  G06F3/041 ,  G11C19/28

Abstract: The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.

公开(公告)号：US10317758B2

公开(公告)日：2019-06-11

申请号：US14409217

申请日：2014-06-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xing Yao

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1339 ,  G02F1/1368

Abstract: An array substrate and a display device having the array substrate are provided. The array substrate comprises a display region and a non-display region disposed at the periphery of the display region. The non-display region comprises a gate driver region (GOA region), which comprises a first patterned metal layer formed on a base substrate, a first insulating layer formed on the first patterned metal layer, a second patterned metal layer formed on the first insulating layer, a second insulating layer covering the second patterned metal layer, and a third patterned metal layer formed at a side of the second insulating layer away from the base substrate. The third patterned metal layer comprises a plurality of metal wires insulated from each other and connected to the first patterned metal layer and the second patterned metal layer respectively by through holes and used as connecting lines between elements of the gate driver.