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28 条记录 (耗时 0.026 秒)

    JTAG interface device of mobile terminal and method thereof
    23.
    发明申请
    JTAG interface device of mobile terminal and method thereof 失效

    公开(公告)号：US20060080577A1

    公开(公告)日：2006-04-13

    申请号：US11221101

    申请日：2005-09-07

    申请人： Bong-Su Kim

    发明人： Bong-Su Kim

    IPC分类号： G06F11/00

    CPC分类号： G01R31/318533 ,  G01R31/31705 ,  G06F11/261 ,  H04W24/00

    摘要： A JTAG interface device capable of effectively debugging a mobile terminal by interfacing the mobile terminal with a JTAG emulator without an additional interface unit by allocating test pins of the JTAG emulator to some pins of a receptacle and then electrically connecting the test pins to the pins, and a method thereof. Accordingly, an operation for debugging the mobile terminal can be easily and effectively performed.

    Recess gate transistor
    24.
    发明授权
    Recess gate transistor 有权
    凹槽门晶体管

    公开(公告)号：US08889539B2

    公开(公告)日：2014-11-18

    申请号：US12332877

    申请日：2008-12-11

    申请人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    发明人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    IPC分类号： H01L21/302 ,  H01L29/66 ,  H01L29/423

    CPC分类号： H01L29/4236 ,  H01L29/66621

    摘要： A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

    摘要翻译： 提供一种形成半导体器件的方法，包括：通过图案化绝缘层在衬底上形成多个硬掩模; 在衬底中形成多个沟槽，每个沟槽具有设置在两个相邻掩模之间并且从底部到上部垂直延伸的沟槽壁; 在硬掩模和沟槽壁上形成绝缘层; 在绝缘层上形成导电层; 蚀刻导电层以形成导电层图案以填充沟槽的底部; 在导电层图案和沟槽壁上沉积缓冲层; 以及用覆盖层填充沟槽的上部。

    RECESS GATE TRANSISTOR
    25.
    发明申请
    RECESS GATE TRANSISTOR 审中-公开
    记忆闸门晶体管

    公开(公告)号：US20120009976A1

    公开(公告)日：2012-01-12

    申请号：US13242724

    申请日：2011-09-23

    申请人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    发明人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    IPC分类号： H04M1/00 ,  G11C11/34 ,  H01L27/088

    CPC分类号： H01L29/4236 ,  H01L29/66621

    摘要： A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

    摘要翻译： 提供一种形成半导体器件的方法，包括：通过图案化绝缘层在衬底上形成多个硬掩模; 在衬底中形成多个沟槽，每个沟槽具有设置在两个相邻掩模之间并且从底部到上部垂直延伸的沟槽壁; 在硬掩模和沟槽壁上形成绝缘层; 在绝缘层上形成导电层; 蚀刻导电层以形成导电层图案以填充沟槽的底部; 在导电层图案和沟槽壁上沉积缓冲层; 以及用覆盖层填充沟槽的上部。

    RECESS GATE TRANSISTOR
    26.
    发明申请
    RECESS GATE TRANSISTOR 有权
    记忆闸门晶体管

    公开(公告)号：US20090261420A1

    公开(公告)日：2009-10-22

    申请号：US12332877

    申请日：2008-12-11

    申请人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    发明人： Ho-In Ryu ,  Bong-Su Kim ,  Dae-Ik Kim ,  Ho-Jun Lee ,  Dae-Young Jang ,  Si-Hyung Lee

    IPC分类号： H01L25/00 ,  H01L21/4763 ,  H01L29/78

    CPC分类号： H01L29/4236 ,  H01L29/66621

    摘要： A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

    摘要翻译： 提供一种形成半导体器件的方法，包括：通过图案化绝缘层在衬底上形成多个硬掩模; 在衬底中形成多个沟槽，每个沟槽具有设置在两个相邻掩模之间并且从底部到上部垂直延伸的沟槽壁; 在硬掩模和沟槽壁上形成绝缘层; 在绝缘层上形成导电层; 蚀刻导电层以形成导电层图案以填充沟槽的底部; 在导电层图案和沟槽壁上沉积缓冲层; 以及用覆盖层填充沟槽的上部。

    JTAG interface device of mobile terminal and method thereof
    27.
    发明授权
    JTAG interface device of mobile terminal and method thereof 失效
    移动终端的JTAG接口设备及其方法

    公开(公告)号：US07577887B2

    公开(公告)日：2009-08-18

    申请号：US11221101

    申请日：2005-09-07

    申请人： Bong-Su Kim

    发明人： Bong-Su Kim

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318533 ,  G01R31/31705 ,  G06F11/261 ,  H04W24/00

    摘要： A JTAG interface device capable of effectively debugging a mobile terminal by interfacing the mobile terminal with a JTAG emulator without an additional interface unit by allocating test pins of the JTAG emulator to some pins of a receptacle and then electrically connecting the test pins to the pins, and a method thereof. Accordingly, an operation for debugging the mobile terminal can be easily and effectively performed.

    摘要翻译： 一种JTAG接口设备，其能够通过将JTAG仿真器的测试引脚分配给插座的一些引脚，然后将测试引脚电连接到引脚，从而通过将移动终端与JTAG仿真器接口而不需要附加的接口单元来有效地调试移动终端， 及其方法。 因此，可以容易且有效地执行用于调试移动终端的操作。

    Method and Apparatus for Registering a Reference Image, and Method and Apparatus for Testing a Pattern Using the Same
    28.
    发明申请
    Method and Apparatus for Registering a Reference Image, and Method and Apparatus for Testing a Pattern Using the Same 审中-公开
    用于注册参考图像的方法和装置，以及用于测试使用其的图案的方法和装置

    公开(公告)号：US20080069429A1

    公开(公告)日：2008-03-20

    申请号：US11777479

    申请日：2007-07-13

    申请人： Byung-Sam Choi ,  Bong-Su Kim ,  Young-Nam Kim ,  Ho-Seong Kang ,  Joung-Soo Kim ,  Jun-Seog Kim

    发明人： Byung-Sam Choi ,  Bong-Su Kim ,  Young-Nam Kim ,  Ho-Seong Kang ,  Joung-Soo Kim ,  Jun-Seog Kim

    IPC分类号： G06K9/00

    CPC分类号： G06K9/64

    摘要： A method of registering a reference image includes obtaining information of layers in a design pattern that is used for forming an actual pattern on a substrate and comparing the information to obtain a difference therebetween. The method further includes obtaining a reference image for testing the actual pattern based on the difference. Thus, the reference image, which is obtained from the design pattern, but not from the actual pattern, may include information on all of the actual patterns on the substrate.

    摘要翻译： 登记参考图像的方法包括获得用于在基板上形成实际图案的设计图案中的层的信息，并比较信息以获得它们之间的差异。 该方法还包括基于差异获得用于测试实际图案的参考图像。 因此，从设计图案而不是从实际图案获得​​的参考图像可以包括关于基板上的所有实际图案的信息。