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21.发明授权Programmable logic device architecture with super-regions having logic regions and a memory region 有权具有逻辑区域和存储区域的超区域的可编程逻辑器件架构公开(公告)号：US06215326B1
公开(公告)日：2001-04-10
申请号：US09266235
申请日：1999-03-10
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译： 可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。 每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。 每个逻辑区域包括可编程逻辑的多个子区域。 每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源 装置。
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公开(公告)号：US6091258A
公开(公告)日：2000-07-18
申请号：US433544
申请日：1999-11-03
IPC分类号： G06F11/20 , G11C29/00 , H03K19/177 , H03K19/003 , H03K19/173
CPC分类号： H03K19/17764 , G11C29/808 , H03K19/17728
摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.
摘要翻译： 提供了诸如可编程逻辑器件之类的逻辑电路的冗余电路。 冗余电路允许通过用冗余逻辑电路替换电路上的故障逻辑区域来修复逻辑电路。 逻辑区域的行和列可以通过行和列交换逻辑地重新映射。 逻辑电路包含动态控制电路，用于以由冗余配置数据定义的顺序将编程数据引导到电路上的各种逻辑区域。 可以使用完全或部分冗余的逻辑区域实现冗余。 可以交换逻辑区域以将部分冗余的逻辑区域重新映射到包含缺陷的逻辑区域。 然后可以使用行或列交换或移位来修复缺陷。 可以通过用冗余半行代替缺陷半行来修复包含折叠行的逻辑区域的逻辑电路。
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23.发明授权Programmable logic device with enhanced multiplexing capabilities in interconnect resources 有权具有增强的互连资源复用能力的可编程逻辑器件公开(公告)号：US06278288B1
公开(公告)日：2001-08-21
申请号：US09574371
申请日：2000-05-19
IPC分类号： G06F738
CPC分类号： H03K19/17752 , H03K19/1737 , H03K19/17736 , H03K19/1778
摘要： A programmable logic integrated circuit device is provided with enhanced capability for dynamically multiplexing signals on the device. Controllable connectors that are provided on the device for connecting any of several connector input signals to a connector output are controlled by control signals that can be programmable selected to be either constant or variable signals. If a control signal is selected to be a variable signal, then the connector controlled by that control signal can be operated as a dynamic multiplexer of the input signals to that connector. The controllable connectors may advantageously be used as the connectors that are employed for allowing several possible signal sources to effectively share a smaller of number of signal drivers.
摘要翻译： 可编程逻辑集成电路器件具有增强的功能，用于在器件上动态地复用信号。 在设备上提供的用于将多个连接器输入信号中的任何一个连接到连接器输出的可控连接器由可编程选择为恒定或可变信号的控制信号控制。 如果控制信号被选择为可变信号，则由该控制信号控制的连接器可以作为到该连接器的输入信号的动态多路复用器来操作。 可控连接器可以有利地用作连接器，其用于允许几个可能的信号源有效地共享更少数量的信号驱动器。
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公开(公告)号：US6034536A
公开(公告)日：2000-03-07
申请号：US982297
申请日：1997-12-01
IPC分类号： G06F11/20 , G11C29/00 , H03K19/177 , H03K19/003 , H03K19/173
CPC分类号： H03K19/17764 , G11C29/808 , H03K19/17728 , H03K19/17736
摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.
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公开(公告)号：US6166559A
公开(公告)日：2000-12-26
申请号：US567825
申请日：2000-05-09
IPC分类号： G06F11/20 , G11C29/00 , H03K19/177 , H03K19/003
CPC分类号： H03K19/17764 , G11C29/808 , H03K19/17728
摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.
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26.发明授权Programmable logic device with enhanced multiplexing capabilities in interconnect resources 失效具有增强的互连资源复用能力的可编程逻辑器件
公开(公告)号：US6121790A
公开(公告)日：2000-09-19
申请号：US87631
申请日：1998-05-29
IPC分类号： H03K19/173 , H03K19/177 , G06F7/38
CPC分类号： H03K19/17752 , H03K19/1737 , H03K19/17736 , H03K19/1778
摘要： A programmable logic integrated circuit device is provided with enhanced capability for dynamically multiplexing signals on the device. Controllable connectors that are provided on the device for connecting any of several connector input signals to a connector output are controlled by control signals that can be programmably selected to be either constant or variable signals. If a control signal is selected to be a variable signal, then the connector controlled by that control signal can be operated as a dynamic multiplexer of the input signals to that connector. The controllable connectors may advantageously be used as the connectors that are employed for allowing several possible signal sources to effectively share a smaller of number of signal drivers.
摘要翻译： 可编程逻辑集成电路器件具有增强的功能，用于在器件上动态地复用信号。 在设备上提供的用于将几个连接器输入信号中的任何一个连接到连接器输出的可控连接器由可编程选择为恒定或可变信号的控制信号控制。 如果控制信号被选择为可变信号，则由该控制信号控制的连接器可以作为到该连接器的输入信号的动态多路复用器来操作。 可控连接器可以有利地用作连接器，其用于允许几个可能的信号源有效地共享更少数量的信号驱动器。
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公开(公告)号：US06937064B1
公开(公告)日：2005-08-30
申请号：US10280723
申请日：2002-10-24
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.
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公开(公告)号：US07432734B2
公开(公告)日：2008-10-07
申请号：US11743625
申请日：2007-05-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.
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公开(公告)号：US07671626B1
公开(公告)日：2010-03-02
申请号：US12202053
申请日：2008-08-29
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/177
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.
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公开(公告)号：US07218133B2
公开(公告)日：2007-05-15
申请号：US11050111
申请日：2005-02-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Timothy Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Timothy Betz
IPC分类号： H03K19/003
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.
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