公开(公告)号：US07218133B2

公开(公告)日：2007-05-15

申请号：US11050111

申请日：2005-02-02

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Timothy Betz

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Timothy Betz

IPC分类号： H03K19/003

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US06937064B1

公开(公告)日：2005-08-30

申请号：US10280723

申请日：2002-10-24

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US07432734B2

公开(公告)日：2008-10-07

申请号：US11743625

申请日：2007-05-02

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US07671626B1

公开(公告)日：2010-03-02

申请号：US12202053

申请日：2008-08-29

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/177

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US20070252617A1

公开(公告)日：2007-11-01

申请号：US11743625

申请日：2007-05-02

申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US20050127944A1

公开(公告)日：2005-06-16

申请号：US11050111

申请日：2005-02-02

申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US07253660B1

公开(公告)日：2007-08-07

申请号：US10305886

申请日：2002-11-27

申请人： Paul Leventis ,  Bruce Pedersen ,  Chris Lane ,  Srinivas Reddy ,  David Lewis

发明人： Paul Leventis ,  Bruce Pedersen ,  Chris Lane ,  Srinivas Reddy ,  David Lewis

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K17/002

摘要： A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals. In another embodiment the multiplexing device includes: a hardwired multiplexer including a plurality of data signal input terminals; and a first plurality of LEs including a first plurality of LE output terminals, where the plurality of data signal input terminals are coupled to the first plurality of LE output terminals.

摘要翻译： 描述多路复用装置。 在一个实施例中，多路复用装置包括：硬连线多路复用器，包括多个输入端; 多个选择端子; 以及至少一个输出端子，其中多个输入端子耦合到多个块输入线或多个功能元件输入端子。 在一个实施例中，多个输入端子被硬连线到多个块输入线或多个功能元件输入端子。 在一个实施例中，多个选择端子耦合到第二多个功能元件输入端子或多个功能元件输出端子。 在一个实施例中，多个块输入线包括多个逻辑阵列块（LAB）线，多个功能元件输入端包括多个逻辑元件（LE）输入端，多个功能元件输出端包括 LE输出端子。 在另一实施例中，多路复用装置包括：硬连线多路复用器，包括多个数据信号输入端; 以及包括第一多个LE输出端子的第一多个LE，其中所述多个数据信号输入端子耦合到所述第一多个LE输出端子。

公开(公告)号：US07061268B1

公开(公告)日：2006-06-13

申请号：US10801242

申请日：2004-03-15

申请人： Andy L. Lee ,  Ninh Ngo ,  Vaughn Betz ,  David Lewis ,  Bruce Pedersen ,  James Schleicher

发明人： Andy L. Lee ,  Ninh Ngo ,  Vaughn Betz ,  David Lewis ,  Bruce Pedersen ,  James Schleicher

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K19/17728

摘要： A logic circuit includes a first series of logic elements. Each logic element has a look-up table (LUT) and a dedicated adder to implement an arithmetic mode in the logic element. The logic circuit also includes a carry chain connecting the first series of logic element, and an initialization circuit connected to the carry chain to initialize the carry chain.

摘要翻译： 逻辑电路包括第一系列逻辑元件。 每个逻辑元件具有查找表（LUT）和专用加法器，以在逻辑元件中实现算术模式。 逻辑电路还包括连接第一系列逻辑元件的进位链和连接到进位链的初始化电路以初始化进位链。

公开(公告)号：US07323902B2

公开(公告)日：2008-01-29

申请号：US11189549

申请日：2005-07-25

申请人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

发明人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

摘要翻译： 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输入端的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

公开(公告)号：US08217678B1

公开(公告)日：2012-07-10

申请号：US12834404

申请日：2010-07-12

申请人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

发明人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

IPC分类号： H03K19/173

CPC分类号： H03K19/177

摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

摘要翻译： 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。