公开(公告)号：US07890738B2

公开(公告)日：2011-02-15

申请号：US11039498

申请日：2005-01-20

申请人： Lee Evan Eisen ,  David Stephen Levitan ,  Francis Patrick O'Connell ,  Wolfram M. Sauer

发明人： Lee Evan Eisen ,  David Stephen Levitan ,  Francis Patrick O'Connell ,  Wolfram M. Sauer

IPC分类号： G06F9/50 ,  G06F9/42

CPC分类号： G06F9/5011 ,  G06F9/3844 ,  G06F9/3851 ,  G06F2209/507 ,  Y02D10/22

摘要： A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is low. The resource control applied may be the number of instruction fetches allocated to the thread or the number of execution time slices. Alternatively, or in combination, the size of a prefetch instruction storage allocated to the thread may be limited. The control condition may be comparison of the number of correct or incorrect speculations to a threshold, comparison of the number of correct to incorrect speculations, or a more complex evaluator such as the size of a ratio of incorrect to total speculations.

摘要翻译： 用于管理用于推测性执行的处理系统资源使用的方法和逻辑装置降低与程序指令的无效推测执行相关联的功率和性能负担。 投机执行效率的度量用于减少分配给线程的资源，同时投机效率低。 应用的资源控制可以是分配给线程的指令获取的数量或执行时间片的数量。 或者或组合地，分配给线程的预取指令存储器的大小可能受到限制。 控制条件可以是正确的或不正确的猜测的数量与阈值的比较，正确到不正确的猜测的数量的比较，或比较复杂的评估者，比如不正确比例与总猜测的比例。

公开(公告)号：US20100050178A1

公开(公告)日：2010-02-25

申请号：US12187351

申请日：2008-08-22

申请人： David Stephen Levitan ,  Jeffrey Richard Summers

发明人： David Stephen Levitan ,  Jeffrey Richard Summers

IPC分类号： G06F9/46

CPC分类号： G06F9/4881 ,  G06F2209/483

摘要： The invention relates to a method and apparatus for execution scheduling of a program thread of an application program and executing the scheduled program thread on a data processing system. The method includes: providing an application program thread priority to a thread execution scheduler; selecting for execution the program thread from a plurality of program threads inserted into the thread execution queue, wherein the program thread is selected for execution using a round-robin selection scheme, and wherein the round-robin selection scheme selects the program thread based on an execution priority associated with the program thread bit; placing the program thread in a data processing execution queue within the data processing system; and removing the program thread from the thread execution queue after a successful execution of the program thread by the data processing system.

摘要翻译： 本发明涉及一种用于执行应用程序的程序线程的调度并在数据处理系统上执行调度程序线程的方法和装置。 该方法包括：向线程执行调度器提供应用程序线程优先级; 从插入到线程执行队列中的多个程序线程中选择执行程序线程，其中使用循环选择方案选择程序线程进行执行，并且其中循环选择方案基于 与程序线程位相关联的执行优先级; 将程序线程放置在数据处理系统内的数据处理执行队列中; 并且在数据处理系统成功执行程序线程之后从线程执行队列中移除程序线程。

公开(公告)号：US07269715B2

公开(公告)日：2007-09-11

申请号：US11050344

申请日：2005-02-03

申请人： Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

发明人： Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

IPC分类号： G06F9/38

CPC分类号： G06F9/3853 ,  G06F9/3802 ,  G06F9/382

摘要： An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current set of instructions are part of a group including a prior set of instructions received in the instruction cache including using a history data structure, wherein the history data structure contains data regarding instructions in the prior set of instructions. Any instructions are grouped into the group with the instruction in response to a determination that the any instructions are part of the group. Instructions in the group units are dispatched to execution using the history data structure, wherein invalid instruction dispatch groupings are avoided.

摘要翻译： 一种改进的方法，装置和计算机指令，用于对在相同大小的集合中处理的指令进行分组。 在指令高速缓存中接收当前的一组指令用于调度。 确定当前指令集中的任何指令是否包括包括使用历史数据结构在指令高速缓存中接收的先前指令集的组的一部分，其中历史数据结构包含关于先前的指令的数据 一套说明 响应于确定任何指令是组的一部分，任何指令被分组到具有指令的组中。 使用历史数据结构将分组单元中的指令调度到执行，其中避免了无效指令分派分组。

公开(公告)号：US5894487A

公开(公告)日：1999-04-13

申请号：US892722

申请日：1997-07-15

申请人： David Stephen Levitan

发明人： David Stephen Levitan

IPC分类号： G06F11/16 ,  G06F11/00

CPC分类号： G06F12/0895 ,  G06F11/073 ,  G06F11/0751 ,  G11C29/38 ,  G11C29/52 ,  G06F2212/1032 ,  G11C15/00

摘要： A system and method for providing error detection in a directory has been disclosed. The method and system include comparing a first group of data and a second group of data to provide a comparison signal and detecting errors in response to the comparison signal.

摘要翻译： 已经公开了用于在目录中提供错误检测的系统和方法。 所述方法和系统包括比较第一组数据和第二组数据以提供比较信号并响应于比较信号检测错误。

公开(公告)号：US5872950A

公开(公告)日：1999-02-16

申请号：US829670

申请日：1997-03-31

申请人： David Stephen Levitan ,  John Stephen Muhich

发明人： David Stephen Levitan ,  John Stephen Muhich

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

摘要： A method and apparatus for managing register renaming in an information handling system that supports out-of-order and speculative instruction execution. Register entries are stored in architected registers, and rename entries are stored in rename registers. Register and rename entries are transferred between the rename and architected registers in response to dispatch of instructions or upon the occurrence of a canceling event, such as a mispredicted branch instruction or an interrupt condition. Rename entries are stored in the rename registers in a round robin fashion and tagged by age. Age order of the rename entries is determined without keeping the rename entries in age order through the method of shifting rename entries to the next rename register each time a rename entry is removed from a rename register. By eliminating shifting of rename entries to maintain age order, a power savings is realized.

摘要翻译： 一种在信息处理系统中管理寄存器重命名的方法和装置，其支持乱序和推测性指令执行。 注册条目存储在架构化的寄存器中，重命名条目存储在重命名寄存器中。 响应于指令的发送或发生诸如错误的分支指令或中断条件的取消事件，在重命名和架构化寄存器之间传送寄存器和重命名条目。 重命名条目以循环方式存储在重命名寄存器中，并按年龄标记。 确定重命名条目的年龄顺序，而不必通过将重命名条目移动到重命名寄存器的每个重命名条目从重命名寄存器中删除的方式将重命名条目按照年龄顺序进行保存。 通过消除重命名条目的移动以维持年龄顺序，实现了省电。

公开(公告)号：US07412620B2

公开(公告)日：2008-08-12

申请号：US11165030

申请日：2005-06-23

申请人： David Stephen Levitan

发明人： David Stephen Levitan

IPC分类号： G06F11/00

CPC分类号： G06F11/2215

摘要： A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not. The data processing system's ability to recover from errors is tested using the directory entry and the cache entry.

摘要翻译： 公开了一种用于测试数据处理系统从高速缓存目录错误中恢复的能力的方法，装置和计算机程序产品。 目录条目存储到缓存目录中。 目录条目包括与该地址标签相关联的地址标签和目录奇偶校验。 缓存条目存储在使用缓存目录访问的缓存中。 缓存条目包括与该信息相关联的信息和缓存奇偶校验。 目录奇偶校验被改变，意味着不平等。 错误的奇偶性意味着与该奇偶校验相关联的地址标签无效。 包含在缓存条目中的信息被更改为不正确的信息。 然而，虽然信息现在不正确，但高速缓存奇偶校验仍然意味着良好的奇偶校验，这意味着数据是好的。 这种良好的平价意味着与奇偶校验相关联的信息是有效的，即使不是。 使用目录条目和缓存条目测试数据处理系统从错误中恢复的能力。

公开(公告)号：US07039768B2

公开(公告)日：2006-05-02

申请号：US10424487

申请日：2003-04-25

申请人： Gregory William Alexander ,  David Stephen Levitan ,  Balaram Sinharoy

发明人： Gregory William Alexander ,  David Stephen Levitan ,  Balaram Sinharoy

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  G06F2212/6082

摘要： A set-associative I-cache that enables early cache hit prediction and correct way selection when the processor is executing instructions of multiple threads having similar EAs. Each way of the I-cache comprises an EA Directory (EA Dir), which includes a series of thread valid bits that are individually assigned to one of the multiple threads. Particular ones of the thread valid bits are set in each EA Dir to indicate when an instruction block the thread is cached within the particular way with which the EA Dir is associated. When a cache line request for a particular thread is received, a cache hit is predicted when the EA of the request matches the EA in the EA Dir and the cache line is selected from the way associated with the EA Dir who has the thread valid bit for that thread set. Early way selection is thus achieved since the way selection only requires a check of the thread valid bits.

摘要翻译： 当处理器执行具有类似EA的多个线程的指令时，能够实现早期缓存命中预测和正确选择方法的集合关联I缓存。 I缓存的每个方式包括EA目录（EA目录），其包括单独分配给多个线程之一的一系列线程有效位。 在每个EA Dir中设置特定的线程有效位，以指示线程是否以EA Dir所关联的特定方式缓存的时间。 当接收到针对特定线程的高速缓存线请求时，当请求的EA与EA Dir中的EA匹配时，预测缓存命中，并且从与具有线程有效位的EA Dir相关联的方式中选择高速缓存行 为该线程集。 因此，由于选择方式仅需要检查线程有效位，因此实现了早期方式选择。

公开(公告)号：US06651162B1

公开(公告)日：2003-11-18

申请号：US09435065

申请日：1999-11-04

申请人： David Stephen Levitan ,  Shashank Nemawarkar ,  Balaram Sinharoy ,  William John Starke

发明人： David Stephen Levitan ,  Shashank Nemawarkar ,  Balaram Sinharoy ,  William John Starke

IPC分类号： G06F926

CPC分类号： G06F9/3806

摘要： A method of prefetching addresses includes the step of accessing a stored instruction using a current address. During the access using the current address, a target address is accessed in a branch target address cache. A stored instruction associated with the target address accessed from the branch target address cache is prefetched and the branch target address is indexed with selected bits from the address accessed from the branch target address cache.

摘要翻译： 预取地址的方法包括使用当前地址访问存储的指令的步骤。 在使用当前地址的访问期间，在分支目标地址缓存中访问目标地址。 与从分支目标地址高速缓存访​​问的目标地址相关联的存储指令被预取，并且从从分支目标地址高速缓存访​​问的地址中选择的位对索引分支目标地址进行索引。

公开(公告)号：US06484256B1

公开(公告)日：2002-11-19

申请号：US09370680

申请日：1999-08-09

申请人： David Stephen Levitan ,  Balaram Sinharoy

发明人： David Stephen Levitan ,  Balaram Sinharoy

IPC分类号： G06F900

CPC分类号： G06F9/3806 ,  G06F9/3848

摘要： Improved conditional branch instruction prediction by detecting branch aliasing in a branch history table. Each entry in an aliasing table is associated with only one of a plurality of conditional branch instructions tracked by the branch history table. Prior to executing a conditional branch instruction, outcome of the execution of the conditional branch instruction is predicted utilizing the branch history table entry associated with the conditional branch instruction. Outcome of the execution of the conditional branch instruction is also predicted utilizing the aliasing table entry associated with the conditional branch instruction. Branch aliasing is detected by comparing the prediction made utilizing the branch history table with the prediction made utilizing the aliasing table. In response to the predictions being different, a determination is made that branch aliasing occurred, and the prediction made utilizing the aliasing table is utilized for predicting the outcome of the execution of the conditional branch instruction.

摘要翻译： 通过检测分支历史表中的分支别名来改进条件分支指令预测。 混叠表中的每个条目仅与由分支历史表跟踪的多个条件转移指令中的一个相关联。 在执行条件转移指令之前，利用与条件转移指令相关联的分支历史表条目来预测条件转移指令的执行结果。 还使用与条件分支指令相关联的混叠表条目来预测条件分支指令的执行的结果。 通过将利用分支历史表进行的预测与利用混叠表进行的预测进行比较来检测分支混叠。 响应于不同的预测，确定发生分支混叠，并且使用利用混叠表进行的预测用于预测条件分支指令的执行结果。

公开(公告)号：US5758143A

公开(公告)日：1998-05-26

申请号：US726963

申请日：1996-10-07

申请人： David Stephen Levitan

发明人： David Stephen Levitan

IPC分类号： G06F9/38

CPC分类号： G06F9/3844

摘要： A method and apparatus for updating a branch history table (BHT) in a processor which resolves multiple branches in a single cycle is disclosed. The method and apparatus utilizes a single write ported BHT that achieves similar performance to a two write ported BHT by selecting only data corresponding to one of the branch instructions for updating the BHT. The data corresponding to the branch instruction for updating the BHT is selected based upon whether a prediction of the instruction path set by the branch instruction was correctly predicted and the state of a corresponding saturation up-down counter in the BHT.

摘要翻译： 公开了一种在单个周期中解决多个分支的处理器中更新分支历史表（BHT）的方法和装置。 该方法和装置利用单个写入端口BHT，其通过仅选择对应于用于更新BHT的分支指令之一的数据来实现与两个写入端口BHT类似的性能。 基于是否正确地预测了由分支指令设置的指令路径的预测以及BHT中相应的饱和上调计数器的状态来选择与用于更新BHT的分支指令相对应的数据。