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1.发明授权公开(公告)号：US08635621B2
公开(公告)日：2014-01-21
申请号：US12187351
申请日：2008-08-22
CPC分类号： G06F9/4881 , G06F2209/483
摘要： The invention relates to a method and apparatus for execution scheduling of a program thread of an application program and executing the scheduled program thread on a data processing system. The method includes: providing an application program thread priority to a thread execution scheduler; selecting for execution the program thread from a plurality of program threads inserted into the thread execution queue, wherein the program thread is selected for execution using a round-robin selection scheme, and wherein the round-robin selection scheme selects the program thread based on an execution priority associated with the program thread bit; placing the program thread in a data processing execution queue within the data processing system; and removing the program thread from the thread execution queue after a successful execution of the program thread by the data processing system.
摘要翻译： 本发明涉及一种用于执行应用程序的程序线程的调度并在数据处理系统上执行调度程序线程的方法和装置。 该方法包括：向线程执行调度器提供应用程序线程优先级; 从插入到线程执行队列中的多个程序线程中选择执行程序线程，其中使用循环选择方案选择程序线程进行执行，并且其中循环选择方案基于 与程序线程位相关联的执行优先级; 将程序线程放置在数据处理系统内的数据处理执行队列中; 并且在数据处理系统成功执行程序线程之后从线程执行队列中移除程序线程。
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公开(公告)号：US20100050178A1
公开(公告)日：2010-02-25
申请号：US12187351
申请日：2008-08-22
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F2209/483
摘要： The invention relates to a method and apparatus for execution scheduling of a program thread of an application program and executing the scheduled program thread on a data processing system. The method includes: providing an application program thread priority to a thread execution scheduler; selecting for execution the program thread from a plurality of program threads inserted into the thread execution queue, wherein the program thread is selected for execution using a round-robin selection scheme, and wherein the round-robin selection scheme selects the program thread based on an execution priority associated with the program thread bit; placing the program thread in a data processing execution queue within the data processing system; and removing the program thread from the thread execution queue after a successful execution of the program thread by the data processing system.
摘要翻译： 本发明涉及一种用于执行应用程序的程序线程的调度并在数据处理系统上执行调度程序线程的方法和装置。 该方法包括：向线程执行调度器提供应用程序线程优先级; 从插入到线程执行队列中的多个程序线程中选择执行程序线程，其中使用循环选择方案选择程序线程进行执行，并且其中循环选择方案基于 与程序线程位相关联的执行优先级; 将程序线程放置在数据处理系统内的数据处理执行队列中; 并且在数据处理系统成功执行程序线程之后从线程执行队列中移除程序线程。
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3.发明授权Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread 失效具有结果数据延迟路径的同时多线程处理器，用于调整输入到相应线程的流水线长度公开(公告)号：US07000233B2
公开(公告)日：2006-02-14
申请号：US10422653
申请日：2003-04-21
IPC分类号： G06F9/46
CPC分类号： G06F9/3867 , G06F9/30189 , G06F9/3851
摘要： An SMT system has a single thread mode and an SMT mode. Instructions are alternately selected from two threads every clock cycle and loaded into the IFAR in a three cycle pipeline of the IFU. If a branch predicted taken instruction is detected in the branch prediction circuit in stage three of the pipeline, then in the single thread mode a calculated address from the branch prediction circuit is loaded into the IFAR on the next clock cycle. If the instruction in the branch prediction circuit detects a branch predicted taken in the SMT mode, then the selected instruction address is loaded into the IFAR on the first clock cycle following branch predicted taken detection. The calculated target address is fed back and loaded into the IFAR in the second clock cycle following branch predicted taken detection. Feedback delay effectively switches the pipeline from three stages to four stages.
摘要翻译： SMT系统具有单线程模式和SMT模式。 每个时钟周期从两个线程交替选择指令，并在IFU的三个循环管道中加载到IFAR中。 如果在流水线的第三级中在分支预测电路中检测到分支预测的指令，则在单线程模式中，来自分支预测电路的计算的地址在下一个时钟周期被加载到IFAR中。 如果分支预测电路中的指令检测到以SMT模式取得的分支预测，则在分支预测采集检测之后，所选择的指令地址在第一时钟周期被加载到IFAR中。 计算的目标地址在分支预测采集检测后的第二个时钟周期中反馈并加载到IFAR中。 反馈延迟有效地将管道从三个阶段切换到四个阶段。
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4.发明授权Apparatus and method for instruction fetching using a multi-port instruction cache directory 失效使用多端口指令缓存目录进行指令读取的装置和方法
公开(公告)号：US5918044A
公开(公告)日：1999-06-29
申请号：US741465
申请日：1996-10-31
CPC分类号： G06F9/3806 , G06F12/0853 , G06F12/0864 , G06F9/3804 , G06F12/1054 , Y02B60/1225
摘要： In an instruction fetch unit for an information handling system which decodes instructions, calculates target addresses of multiple branch instructions, and resolves multiple branch instructions in parallel instead of sequentially, the critical path through a multiple way set associative instruction cache is through a directory and compare circuit which selects which way instructions will be retrieved. This patch is known as the late select path. A multi-ported effective address (EA) directory is provided and is accessed prior to selection of a fetch address which fetches the next set of instructions from the cache. In this manner, the time required for the late select path can be reduced.
摘要翻译： 在用于解码指令的信息处理系统的指令获取单元中，计算多个分支指令的目标地址，并行而不是依次解析多个分支指令，通过多路组合关联指令高速缓存的关键路径通过目录并进行比较 选择哪种方式指令将被检索的电路。 这个补丁被称为晚期选择路径。 提供多端口有效地址（EA）目录，并且在选择从高速缓存取出下一组指令的获取地址之前被访问。 以这种方式，可以减少延迟选择路径所需的时间。
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5.发明授权Method and system of addressing which minimize memory utilized to store logical addresses by storing high order bits within a register 失效寻址方法和系统，通过在寄存器中存储高阶位来最小化用于存储逻辑地址的存储器
公开(公告)号：US5765221A
公开(公告)日：1998-06-09
申请号：US767568
申请日：1996-12-16
CPC分类号： G06F9/342 , G06F9/30094 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/3557 , G06F9/3802
摘要： An improved method of addressing within a pipelined processor having an address bit width of m+n bits is disclosed, which includes storing m high order bits corresponding to a first range of addresses, which encompasses a selected plurality of data executing within the pipelined processor. The n low order bits of addresses associated with each of the selected plurality of data are also stored. After determining the address of a subsequent datum to be executed within the processor, the subsequent datum is fetched. In response to fetching a subsequent datum having an address outside of the first range of addresses, a status register is set to a first of two states to indicate that an update to the first address register is required. In response to the status register being set to the second of the two states, the subsequent datum is dispatched for execution within the pipelined processor. The n low order bits of the subsequent datum are then stored, such that memory required to store addresses of instructions executing within the pipelined processor is thereby decreased.
摘要翻译： 公开了一种具有地址位宽度为m + n位的流水线处理器内的寻址改进方法，其包括存储对应于第一地址范围的m个高位，其包含在流水线处理器内执行的选定的多个数据。 还存储与所选择的多个数据中的每一个相关联的n个低位地址。 在确定要在处理器中执行的后续数据的地址之后，获取随后的数据。 响应于获取具有在第一地址范围之外的地址的后续数据，状态寄存器被设置为两种状态中的第一状态，以指示需要对第一地址寄存器的更新。 响应于将状态寄存器设置为两个状态中的第二个状态，随后的数据被调度以在流水线处理器内执行。 然后存储随后数据的n个低位，从而减少了在流水线处理器内执行的指令的存储地址所需的存储器。
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6.发明申请公开(公告)号：US20080276080A1
公开(公告)日：2008-11-06
申请号：US12171370
申请日：2008-07-11
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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7.发明授权Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush 失效禁止指令缓冲区直到重新循环被拒绝的前导和分支指令，以避免错误预测冲洗公开(公告)号：US07254700B2
公开(公告)日：2007-08-07
申请号：US11056512
申请日：2005-02-11
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3814 , G06F9/3842 , G06F9/3844 , G06F9/3861
摘要： Systems and methods for handling the event of a wrong branch prediction and an instruction rejection in a digital processor are disclosed. More particularly, hardware and software are disclosed for detecting a condition where a branch instruction was mispredicted and an instruction that preceded the branch instruction is rejected after the branch instruction is executed. When the condition is detected, the branch instruction and rejected instruction are recirculated for execution. Until, the branch instruction is re-executed, control circuitry can prevent instructions from being received into an instruction buffer that feeds instructions to the execution units of the processor by fencing the instruction buffer from the fetcher. The instruction fetcher may continue fetching instructions along the branch target path into a local cache until the fence is dropped.
摘要翻译： 公开了用于处理数字处理器中错误分支预测和指令拒绝的事件的系统和方法。 更具体地，公开了用于检测分支指令被错误预测的条件并且在执行分支指令之后拒绝分支指令之前的指令的硬件和软件。 当检测到条件时，分支指令和拒绝指令被再循环以执行。 直到分支指令被重新执行为止，控制电路可以防止指令被接收到指令缓冲器中，该指令缓冲器通过从提取器中击打指令缓冲器来将指令馈送到处理器的执行单元。 指令读取器可以继续沿着分支目标路径获取指令到本地高速缓存中，直到栅栏被丢弃。
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8.发明授权Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment 失效通过在同时多线程处理环境中逻辑分割分支历史表和预测目标地址缓存来进行线程专用分支预测公开(公告)号：US07120784B2
公开(公告)日：2006-10-10
申请号：US10425064
申请日：2003-04-28
CPC分类号： G06F9/3806 , G06F9/30189 , G06F9/3844 , G06F9/3851
摘要： Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.
摘要翻译： 分支预测逻辑被增强以提供用于某些条件的监视功能，其指示使用单独的BHT和预测的目标地址高速缓存将为分支预测提供更好的结果。 分支预测逻辑通过逻辑分割BHT和计数高速缓存来响应监视条件的发生，使得一半的地址空间被分配给第一个线程，而后半部分被分配给下一个线程。 属于第一个线程的预测生成的地址然后被定向到分配给该线程的数组的一半，并且属于第二个线程的预测生成的地址被定向到分配给该线程的数组的下一半 第二线程。 为了拆分阵列，阵列中的最高位用于唯一标识第一和第二个线程的地址。
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公开(公告)号：US06279105B1
公开(公告)日：2001-08-21
申请号：US09173039
申请日：1998-10-15
IPC分类号： G06F1300
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3861
摘要： In a branch instruction target address cache, an entry associated with a fetched block of instructions includes a target address of a branch instruction residing in the next sequential block of instructions. The entry will include a sequential address associated with the branch instruction and a prediction of whether the target address is taken or not taken.
摘要翻译： 在分支指令目标地址高速缓存中，与获取的指令块相关联的条目包括驻留在下一个顺序指令块中的分支指令的目标地址。 条目将包括与分支指令相关联的顺序地址以及是否采取目标地址的预测。
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10.发明授权Self-checking content-addressable memory and method of operation for detecting multiple selected word lines 失效自检内容可寻址存储器和检测多个选定字线的操作方法
公开(公告)号：US5796758A
公开(公告)日：1998-08-18
申请号：US727334
申请日：1996-10-08
CPC分类号： G06F11/1064 , G06F17/30982 , G11C15/00 , H03M13/51
摘要： A Content Addressable Memory (CAM) includes a plurality of conventional CAM cells arranged in rows and columns, the CAM cells being coupled together by word lines and bit lines for reading from and writing information into the CAM cells. Each CAM cell in a row is connected to a match line which provides an indication when an input word on the bit lines matches the contents of the cells coupled to the match line. A combinatorial logic circuit including a parity generator is coupled to the word lines and provides an indication when multiple words have been selected by an input word. The combinatorial logic circuit includes an OR circuit providing a first input to an AND circuit and a parity generator providing a second input to the AND which only provides an output when multiple word lines have been selected by an input word.
摘要翻译： 内容可寻址存储器（CAM）包括以行和列排列的多个常规CAM单元，CAM单元通过字线和位线耦合在一起，用于从CAM单元读取和写入信息。 一行中的每个CAM单元连接到匹配线，当匹配位线上的输入字与耦合到匹配线的单元的内容匹配时，该匹配线提供指示。 包括奇偶校验发生器的组合逻辑电路被耦合到字线，并且当多个字被输入字选择时提供指示。 组合逻辑电路包括向AND电路提供第一输入的OR电路和向AND提供第二输入的奇偶校验发生器，当输入字已经选择了多个字线时，该AND只提供输出。
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