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1.发明授权Method and logical apparatus for managing processing system resource use for speculative execution 失效用于管理用于投机执行的处理系统资源使用的方法和逻辑装置公开(公告)号：US07890738B2
公开(公告)日：2011-02-15
申请号：US11039498
申请日：2005-01-20
CPC分类号： G06F9/5011 , G06F9/3844 , G06F9/3851 , G06F2209/507 , Y02D10/22
摘要： A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is low. The resource control applied may be the number of instruction fetches allocated to the thread or the number of execution time slices. Alternatively, or in combination, the size of a prefetch instruction storage allocated to the thread may be limited. The control condition may be comparison of the number of correct or incorrect speculations to a threshold, comparison of the number of correct to incorrect speculations, or a more complex evaluator such as the size of a ratio of incorrect to total speculations.
摘要翻译： 用于管理用于推测性执行的处理系统资源使用的方法和逻辑装置降低与程序指令的无效推测执行相关联的功率和性能负担。 投机执行效率的度量用于减少分配给线程的资源，同时投机效率低。 应用的资源控制可以是分配给线程的指令获取的数量或执行时间片的数量。 或者或组合地，分配给线程的预取指令存储器的大小可能受到限制。 控制条件可以是正确的或不正确的猜测的数量与阈值的比较，正确到不正确的猜测的数量的比较，或比较复杂的评估者，比如不正确比例与总猜测的比例。
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2.发明授权Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor 失效用于在超标量微处理器中同步并行管线的方法和装置公开(公告)号：US06385719B1
公开(公告)日：2002-05-07
申请号：US09345719
申请日：1999-06-30
IPC分类号： G06F938
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the branch pipeline are assigned a concatenated version (group tag concatenated with instruction lane) of the transfer tag which is used to match on requests to flush any newer instructions. All potential instruction or Internal Operation latches in the decode pipeline must perform a match and if a match is encountered, all valid bits associated with newer instructions or internal operations upstream from the match are cleared. The transfer tag representing the next instruction to be processed in the branch pipeline is passed to the Instruction Dispatch Unit. The Instruction Dispatch Unit queries the branch pipeline to compare its transfer tag with transfer tags of instructions in the branch pipeline. If the transfer tag matches a branch instruction tag the Instruction Decode Unit is stalled until the branch instruction is processed thus, providing a synchronizing method for the parallel pipelines.
摘要翻译： 传送标签由指令提取单元生成，并在指令流水线中传送给解码单元，每个指令组由读取器在分支预测期间取出。 为分支流水线提取的组中的单独指令被分配用于匹配在刷新任何较新指令的请求上的传送标签的级联版本（组标签与指令通道连接）。 解码流水线中的所有潜在指令或内部操作锁存器必须执行匹配，并且如果遇到匹配，将清除与较新指令相关联的所有有效位或匹配上游的内部操作。 表示在分支管线中要处理的下一条指令的传送标签被传递到指令调度单元。 指令调度单元查询分支流水线以将其传输标签与分支流水线中的指令的传输标签进行比较。 如果转移标签与分支指令标签匹配，则指令解码单元停止，直到处理分支指令为止，为并行管线提供同步方法。
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3.发明申请公开(公告)号：US20080276080A1
公开(公告)日：2008-11-06
申请号：US12171370
申请日：2008-07-11
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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公开(公告)号：US07984280B2
公开(公告)日：2011-07-19
申请号：US12171370
申请日：2008-07-11
IPC分类号： G06F9/00
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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公开(公告)号：US08943301B2
公开(公告)日：2015-01-27
申请号：US13101650
申请日：2011-05-05
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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公开(公告)号：US20110213951A1
公开(公告)日：2011-09-01
申请号：US13101650
申请日：2011-05-05
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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7.发明授权Methods and systems for storing branch information in an address table of a processor 失效用于将分支信息存储在处理器的地址表中的方法和系统公开(公告)号：US07426631B2
公开(公告)日：2008-09-16
申请号：US11049014
申请日：2005-02-02
CPC分类号： G06F9/3806
摘要： Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法和系统。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。
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8.发明授权Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread 失效具有结果数据延迟路径的同时多线程处理器，用于调整输入到相应线程的流水线长度公开(公告)号：US07000233B2
公开(公告)日：2006-02-14
申请号：US10422653
申请日：2003-04-21
IPC分类号： G06F9/46
CPC分类号： G06F9/3867 , G06F9/30189 , G06F9/3851
摘要： An SMT system has a single thread mode and an SMT mode. Instructions are alternately selected from two threads every clock cycle and loaded into the IFAR in a three cycle pipeline of the IFU. If a branch predicted taken instruction is detected in the branch prediction circuit in stage three of the pipeline, then in the single thread mode a calculated address from the branch prediction circuit is loaded into the IFAR on the next clock cycle. If the instruction in the branch prediction circuit detects a branch predicted taken in the SMT mode, then the selected instruction address is loaded into the IFAR on the first clock cycle following branch predicted taken detection. The calculated target address is fed back and loaded into the IFAR in the second clock cycle following branch predicted taken detection. Feedback delay effectively switches the pipeline from three stages to four stages.
摘要翻译： SMT系统具有单线程模式和SMT模式。 每个时钟周期从两个线程交替选择指令，并在IFU的三个循环管道中加载到IFAR中。 如果在流水线的第三级中在分支预测电路中检测到分支预测的指令，则在单线程模式中，来自分支预测电路的计算的地址在下一个时钟周期被加载到IFAR中。 如果分支预测电路中的指令检测到以SMT模式取得的分支预测，则在分支预测采集检测之后，所选择的指令地址在第一时钟周期被加载到IFAR中。 计算的目标地址在分支预测采集检测后的第二个时钟周期中反馈并加载到IFAR中。 反馈延迟有效地将管道从三个阶段切换到四个阶段。
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9.发明授权Apparatus and method for instruction fetching using a multi-port instruction cache directory 失效使用多端口指令缓存目录进行指令读取的装置和方法
公开(公告)号：US5918044A
公开(公告)日：1999-06-29
申请号：US741465
申请日：1996-10-31
CPC分类号： G06F9/3806 , G06F12/0853 , G06F12/0864 , G06F9/3804 , G06F12/1054 , Y02B60/1225
摘要： In an instruction fetch unit for an information handling system which decodes instructions, calculates target addresses of multiple branch instructions, and resolves multiple branch instructions in parallel instead of sequentially, the critical path through a multiple way set associative instruction cache is through a directory and compare circuit which selects which way instructions will be retrieved. This patch is known as the late select path. A multi-ported effective address (EA) directory is provided and is accessed prior to selection of a fetch address which fetches the next set of instructions from the cache. In this manner, the time required for the late select path can be reduced.
摘要翻译： 在用于解码指令的信息处理系统的指令获取单元中，计算多个分支指令的目标地址，并行而不是依次解析多个分支指令，通过多路组合关联指令高速缓存的关键路径通过目录并进行比较 选择哪种方式指令将被检索的电路。 这个补丁被称为晚期选择路径。 提供多端口有效地址（EA）目录，并且在选择从高速缓存取出下一组指令的获取地址之前被访问。 以这种方式，可以减少延迟选择路径所需的时间。
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10.发明授权Method and system of addressing which minimize memory utilized to store logical addresses by storing high order bits within a register 失效寻址方法和系统，通过在寄存器中存储高阶位来最小化用于存储逻辑地址的存储器
公开(公告)号：US5765221A
公开(公告)日：1998-06-09
申请号：US767568
申请日：1996-12-16
CPC分类号： G06F9/342 , G06F9/30094 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/3557 , G06F9/3802
摘要： An improved method of addressing within a pipelined processor having an address bit width of m+n bits is disclosed, which includes storing m high order bits corresponding to a first range of addresses, which encompasses a selected plurality of data executing within the pipelined processor. The n low order bits of addresses associated with each of the selected plurality of data are also stored. After determining the address of a subsequent datum to be executed within the processor, the subsequent datum is fetched. In response to fetching a subsequent datum having an address outside of the first range of addresses, a status register is set to a first of two states to indicate that an update to the first address register is required. In response to the status register being set to the second of the two states, the subsequent datum is dispatched for execution within the pipelined processor. The n low order bits of the subsequent datum are then stored, such that memory required to store addresses of instructions executing within the pipelined processor is thereby decreased.
摘要翻译： 公开了一种具有地址位宽度为m + n位的流水线处理器内的寻址改进方法，其包括存储对应于第一地址范围的m个高位，其包含在流水线处理器内执行的选定的多个数据。 还存储与所选择的多个数据中的每一个相关联的n个低位地址。 在确定要在处理器中执行的后续数据的地址之后，获取随后的数据。 响应于获取具有在第一地址范围之外的地址的后续数据，状态寄存器被设置为两种状态中的第一状态，以指示需要对第一地址寄存器的更新。 响应于将状态寄存器设置为两个状态中的第二个状态，随后的数据被调度以在流水线处理器内执行。 然后存储随后数据的n个低位，从而减少了在流水线处理器内执行的指令的存储地址所需的存储器。
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