公开(公告)号：US06031415A

公开(公告)日：2000-02-29

申请号：US733820

申请日：1996-10-18

Applicant: Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

IPC: H04J13/00 ,  H03H17/02 ,  H04B1/7093 ,  H03K5/00 ,  H03D1/00

CPC classification number: H03H17/0254 ,  H04B1/707

Abstract: The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.

Abstract translation: 本发明提供了可用于处理小尺寸电路中的长P / N码的匹配滤波器电路。 根据本发明的匹配滤波器电路在所提出的发明中执行以下处理：i）采样和保持电路乘以长码的数量的一部分; ii）乘法器与来自第一乘法器寄存器的采样和保持电路并联输入，其可以容纳与i）中的采样和保持电路的数量一样多的PN码; iii）当存在要被顺序使用的PN码为PN码时，PN码存储在第一乘法器电阻相同容量的第二乘法器寄存器中; 和iv）第二乘法器寄存器中的PN码并行发送到第一乘法器寄存器。 PN码以串行方式输入到第二个乘法器寄存器。

公开(公告)号：US5926512A

公开(公告)日：1999-07-20

申请号：US735787

申请日：1996-10-23

Applicant: Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H04J13/00 ,  H03H11/04 ,  H03H17/02 ,  H03H19/00 ,  H04B1/7093 ,  H03D1/00 ,  H04L27/06

CPC classification number: H03H11/04 ,  H03H17/0254 ,  Y02B60/50

Abstract: A matched filter circuit for mobile communications is disclosed. The circuit may be fabricated in a small size using large-scale integration and can perform high-speed processing and double sampling at a reduced rate of power consumption. In one embodiment, a plurality of sampling and holding circuits each including a switch are divided into two groups. A control circuit successively closes one of the switches in the first group every chip time, while successively closing one of the switches in the second group at a timing shifted by one-half chip time from that of the first group, thereby enabling a double-sampling operation. Outputs of the sampling and holding circuits in each group are summed by an analog circuit with a high degree of linearity, resulting in a high processing speed combined with a reduced circuit size and power consumption.

Abstract translation: 公开了一种用于移动通信的匹配滤波器电路。 该电路可以使用大规模集成在小尺寸上制造，并且可以以降低的功率消耗来执行高速处理和双重采样。 在一个实施例中，每个包括开关的多个采样和保持电路被分成两组。 控制电路在每个码片时间连续地闭合第一组中的一个开关，同时以与第一组相比半个码片时间偏移的时间顺序地关闭第二组中的一个开关，由此， 抽样操作。 每个组中的采样和保持电路的输出由具有高线性度的模拟电路相加，导致高处理速度以及减小的电路尺寸和功耗。

公开(公告)号：US5910948A

公开(公告)日：1999-06-08

申请号：US955613

申请日：1997-10-22

Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H04B1/707 ,  H04B1/708 ,  H04B1/7083 ,  H04B7/26 ,  H04J13/00 ,  H04L7/00 ,  H04W36/00 ,  H04W48/18 ,  H04W56/00 ,  H04B7/216

CPC classification number: H04W48/18 ,  H04B1/70735 ,  H04B1/70775 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7093 ,  H04B1/7117 ,  H04B2201/70702 ,  H04W36/00

Abstract: The present invention realizes a rapid and efficient cell search and small-size instrument for an asynchronous DS-CDMA cellular system. This cell search detects the correlation between the received signal and the short code of the control channel, and matched filter 22 detects the maximum electric power correlation peak location. Next, using correlators 28-1 to 28-n which are parallelly set in a plurality for RAKE processing with plurality, identifies the long code that is set in the system with the detected long code timing. After the long code is synchronized, a multipath signal is received using 28-1 to 28-n, and the data is judged by RAKE processing. When peripheral cell search is executed, after long code timing is detected by using matched filter 22, the long code of the candidate peripheral cell is designated using the same matched filter. Handover is safely realized by receiving the signal from the connected base station by correlators 28-1 to 28-n, and the base station signal through handover by 22.

Abstract translation: 本发明实现了用于异步DS-CDMA蜂窝系统的快速且有效的小区搜索和小尺寸仪器。 该小区搜索检测接收信号与控制信道的短码之间的相关性，匹配滤波器22检测最大功率相关峰位置。 接下来，使用多个并行设置为用于RAKE处理的多个的相关器28-1至28-n识别具有检测到的长码定时的系统中设置的长码。 在长代码同步之后，使用28-1至28-n接收多路径信号，并且通过RAKE处理来判断数据。 当执行外围小区搜索时，在通过使用匹配滤波器22检测长码定时之后，使用相同的匹配滤波器来指定候选周边小区的长码。 通过由相关器28-1至28-n接收来自所连接的基站的信号，以及通过22次切换的基站信号来安全地实现切换。

公开(公告)号：US5790590A

公开(公告)日：1998-08-04

申请号：US740672

申请日：1996-10-31

Applicant: Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H03H15/00 ,  H03H17/02 ,  H04B1/7093 ,  H04J13/00 ,  H04B15/00

CPC classification number: H04B1/7093

Abstract: The present invention has an object to provide a matched filter circuit which is possible to synchronize a spreading code with an input signal. A matched filter according to the present invention samples input signal in response to three clocks from the first to the third shifted by a half cycle of a sampling signal so as to judge whether the sampling clock is ahead or behind of the input signal according to signs of input signal sampled. One clock is selected to be the sampling clock.

Abstract translation: 本发明的目的是提供一种可以使扩展码与输入信号同步的匹配滤波器电路。 根据本发明的匹配滤波器响应于从第一到第三的三个时钟采样输入信号，移位了采样信号的半个周期，以便根据符号判断采样时钟是否在输入信号的前面或后面 的输入信号采样。 选择一个时钟作为采样时钟。

公开(公告)号：US5737368A

公开(公告)日：1998-04-07

申请号：US715321

申请日：1996-09-17

Applicant: Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC: H04J13/00 ,  G11C27/02 ,  H03H11/04 ,  H03H17/02 ,  H04B1/7093 ,  H03D1/00

CPC classification number: H03H11/04 ,  H03H17/0254

Abstract: A matched filter contains a plurality of auxiliary sampling and holding circuits in addition to a main sampling and holding circuit containing multiple unit sampling and holding circuits. An auxiliary sampling and holding circuit is used to hold an input voltage, which would ordinarily be held by a unit sampling and holding circuit, when the unit sampling and holding circuit is being refreshed. By holding a part of the analog input voltage in the auxiliary sampling and holding circuits, refreshing is performed without decreasing the overall calculation speed.

Abstract translation: 除了包含多个单元采样和保持电路的主采样和保持电路之外，匹配滤波器还包含多个辅助采样和保持电路。 当单元采样和保持电路被刷新时，辅助采样和保持电路用于保持通常由单元采样和保持电路保持的输入电压。 通过将模拟输入电压的一部分保持在辅助采样和保持电路中，在不降低总体计算速度的情况下执行刷新。

公开(公告)号：US06563373B1

公开(公告)日：2003-05-13

申请号：US09165301

申请日：1998-10-02

Applicant: Guoliang Shou ,  Kunihiko Suzuki ,  Changming Zhou

Inventor： Guoliang Shou ,  Kunihiko Suzuki ,  Changming Zhou

IPC: H03H1502

CPC classification number: H04B1/7093 ,  H03H11/04

Abstract: An analog calculation circuit in a filter circuit is corrected in the calculation error by estimating the error from a calculation result of known inputs and known multiplier. A multiplier is changed according to the estimated error. The filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.

Abstract translation: 滤波器电路中的模拟计算电路通过从已知输入和已知乘数的计算结果估计误差来校正计算误差。 根据估计的误差改变乘数。 滤波电路在输入侧具有电压 - 电流转换器，在输出侧具有电流 - 电压转换器，并且在其中执行电流计算。

公开(公告)号：US06539009B1

公开(公告)日：2003-03-25

申请号：US09195162

申请日：1998-11-18

Applicant: Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H04B1707

CPC classification number: H04B1/707

Abstract: A plurality of sets of spreading code sequences are stored in registers and selectively supplied to matched filters. The soft-handover, multi-code processing and long-delay paths can be processed by a small circuit.

Abstract translation: 多组扩展码序列被存储在寄存器中并选择性地提供给匹配的滤波器。 软切换，多码处理和长延迟路径可以由小电路处理。

公开(公告)号：US06426949B1

公开(公告)日：2002-07-30

申请号：US09098357

申请日：1998-06-17

Applicant: Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

Inventor： Changming Zhou ,  Xuping Zhou ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC: H04B7216

CPC classification number: H04B1/707 ,  H04B1/7115 ,  H04B2201/70701

Abstract: A signal reception apparatus for DS-CDMA communication system having a complex matched filter for despreading a received signal into I- and Q-components Di and Dq of despread signal. Dj and Dq are input to a path selection portion 13 for extracting a phase error in a pilot symbol block of the despread signal. A phase compensation signal is calculated according to the phase error in the portion 13. An information symbol is compensated according to the phase compensation signal. An electrical power is calculated from an average of the phase compensation signal of several slots for selecting paths to be received. The selected paths are combined with phase synchronized by a rake combiner 14.

Abstract translation: 一种具有复数匹配滤波器的DS-CDMA通信系统的信号接收装置，用于将接收信号解扩展成解扩信号的I和Q分量Di和Dq。 Dj和Dq被输入到路径选择部分13，用于提取去扩展信号的导频符号块中的相位误差。 根据部分13中的相位误差来计算相位补偿信号。根据相位补偿信号补偿信息符号。 从用于选择要接收的路径的几个时隙的相位补偿信号的平均值计算电功率。 所选择的路径与由耙式组合器14相位同步的组合。

公开(公告)号：US06388583B1

公开(公告)日：2002-05-14

申请号：US09588613

申请日：2000-06-06

Applicant: Biqi Long ,  Changming Zhou

Inventor： Biqi Long ,  Changming Zhou

IPC: H03M700

CPC classification number: H04J13/10

Abstract: The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.

Abstract translation: 本发明提供了一种方法和电路，用于产生能够在较短的等待时间内在反向信道上发送长码的代码。 该方法涉及对应于序列M或长码周期的开始之间的移位量，以及每个定时到多个掩蔽数据的组合; 确定用于响应于在尽可能快的时间点的传输请求开始生成长码的定时的掩蔽数据的组合; 以及根据掩蔽数据移动矢量的初始值。

公开(公告)号：US6038250A

公开(公告)日：2000-03-14

申请号：US3509

申请日：1998-01-06

Applicant: Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

Inventor： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

IPC: H04B1/707 ,  H04B1/7075 ,  H04B7/26 ,  H04W56/00 ,  H04W76/02 ,  H04B7/216

CPC classification number: H04B1/7077 ,  H04B1/7083 ,  H04B1/70735 ,  H04B1/70751 ,  H04B2201/70702

Abstract: Cells are searched at a high speed using an initial synchronization method and a receiver for a DS-CDMA inter base station asynchronous cellular system. A base band received signal is input to a matched filter and is correlated with a spread code supplied from a spread code generator. A signal electric power calculator calculates the electric power of the correlation output of the matched filter, and outputs the result to a long code synchronization timing determiner, a threshold value calculator, and a long code identifier. During the initial cell search, the spread code generator outputs a short code #0 that is common to the control channel of each of the base stations. After the long code synchronization timing has been determined, each of the segments of the N chips which constitutes a portion of the synthesized spread code sequence synthesized from a long code #i that is unique to each of the base stations and the short code #0 is sequentially replaced and output.

Abstract translation: 使用初始同步方法和用于DS-CDMA基站间异步蜂窝系统的接收机以高速搜索小区。 基带接收信号被输入到匹配滤波器，并与从扩展码发生器提供的扩展码相关。 信号电力计算器计算匹配滤波器的相关输出的功率，并将结果输出到长码同步定时确定器，阈值计算器和长码标识符。 在初始小区搜索期间，扩频码发生器输出每个基站的控制信道共同的短码＃0。 在确定了长代码同步定时之后，构成从每个基站唯一的长码#i合成的合成扩展码序列的一部分的N个码片的每个片段和短码＃0 顺序更换并输出。