APPARATUS, SYSTEM, AND METHOD FOR CAPACITANCE CHANGE NON-VOLATILE MEMORY DEVICE
    21.
    发明申请
    APPARATUS, SYSTEM, AND METHOD FOR CAPACITANCE CHANGE NON-VOLATILE MEMORY DEVICE 审中-公开
    装置,系统和电容改变非易失性存储器件的方法

    公开(公告)号:US20110278657A1

    公开(公告)日:2011-11-17

    申请号:US12777866

    申请日:2010-05-11

    摘要: An apparatus, system, and method for a capacitance change non-volatile memory device. The apparatus may include a substrate, a source region in the substrate, a drain region in the substrate, a tunnel oxide layer on the substrate substantially between the source region and the drain region, a floating gate layer on the tunnel oxide layer, a resistance changing material layer on the floating gate layer, and a control gate on the resistance changing material layer.

    摘要翻译: 一种用于电容改变非易失性存储器件的装置,系统和方法。 该装置可以包括衬底,衬底中的源极区域,衬底中的漏极区域,基本上在源极区域和漏极区域之间的衬底上的隧道氧化物层,隧道氧化物层上的浮动栅极层,电阻 在浮动栅极层上的改变材料层,以及电阻变化材料层上的控制栅极。

    Memory having cap structure for magnetoresistive junction and method for structuring the same
    22.
    发明授权
    Memory having cap structure for magnetoresistive junction and method for structuring the same 失效
    具有用于磁阻结的帽结构的存储器及其结构化方法

    公开(公告)号:US07602032B2

    公开(公告)日:2009-10-13

    申请号:US11117854

    申请日:2005-04-29

    IPC分类号: H01L29/82

    CPC分类号: G11C11/15 H01L43/08 H01L43/12

    摘要: A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed over an upper magnetic layer of a magnetoresistive junction (MTJ/MCJ) layered structure and a hardmask layer formed over said etch stop layer, wherein said etch stop layer is selected from a material such that an etch chemistry used for removing said hardmask layer has selectivity against etching said etch stop layer material. In a method of opening the hardmask layer, an etch process to remove exposed portions of the hardmask layer is implemented, where the etch process terminates on the etch stop layer.

    摘要翻译: 公开了一种存储器和制造存储器的方法。 在一个实施例中,存储器包括用于磁阻随机存取存储器件的盖结构,其包括形成在磁阻结(MTJ / MCJ)分层结构的上磁层上的蚀刻停止层和形成在所述蚀刻停止层上的硬掩模层, 其中所述蚀刻停止层选自材料,使得用于去除所述硬掩模层的蚀刻化学性质对蚀刻所述蚀刻停止层材料具有选择性。 在打开硬掩模层的方法中,实现去除硬掩模层的暴露部分的蚀刻工艺,其中蚀刻工艺在蚀刻停止层上终止。

    Method of forming dual interconnects in manufacturing MRAM cells
    24.
    发明申请
    Method of forming dual interconnects in manufacturing MRAM cells 有权
    在制造MRAM单元中形成双互连的方法

    公开(公告)号:US20070123023A1

    公开(公告)日:2007-05-31

    申请号:US11289787

    申请日:2005-11-30

    IPC分类号: H01L21/4763

    CPC分类号: H01L43/12

    摘要: A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on the magnetoresistive junction element; a second non-conductive layer above the first non-conductive layer in regions over the hard mask and a second of the metallic lines; a third non-conductive layer disposed above the hard mask; and a fourth non-conductive layer disposed on the third non-conductive layer. The method further includes partially opening first and second trenches to uncover the second non-conductive layer above the hard mask and second metallic line, respectively; fully opening the first and second trenches to uncover the hard mask and second metallic line, respectively; and filling the first and second trenches with conductive material.

    摘要翻译: 在磁阻存储单元中形成双互连的方法包括:提供中间产品,包括:包括金属线的金属化层; 通过第一非导电层导电地连接到第一金属线的磁阻结点; 设置在磁阻接合元件上的金属硬掩模; 在所述硬掩模上的区域中的所述第一非导电层上方的第二非导电层和所述金属线中的第二非导电层; 设置在硬掩模上方的第三非导电层; 以及设置在所述第三非导电层上的第四非导电层。 该方法还包括部分地打开第一和第二沟槽以分别露出硬掩模和第二金属线上方的第二非导电层; 分别完全打开第一和第二沟槽以揭开硬掩模和第二金属线; 以及用导电材料填充第一和第二沟槽。

    Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition
    25.
    发明授权
    Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition 失效
    在磁堆叠沉积之前图案化磁存储单元底电极的方法

    公开(公告)号:US06849465B2

    公开(公告)日:2005-02-01

    申请号:US10600920

    申请日:2003-06-20

    CPC分类号: H01L43/12

    摘要: A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.

    摘要翻译: 图案化用于磁存储单元的底电极的方法。 在沉积磁隧道结(MTJ)材料层的软层之前,将底部电极图案化,从而防止在软层的侧壁上形成栅栏,这可能导致随后形成的磁记录的导线的短路 设备。 牺牲掩模用于对底部电极材料进行图案化,并且在底部电极材料的图案化期间消耗或去除牺牲掩模的至少一部分。 然后使用硬掩模沉积和图案化软层。