公开(公告)号：US20140065058A1

公开(公告)日：2014-03-06

申请号：US13605536

申请日：2012-09-06

申请人： ByungChun PARK ,  Woosik KIM ,  HoSuk SHIN ,  Soonho AHN ,  Hong Kyu PARK ,  Joon Hyun CHANG

发明人： ByungChun PARK ,  Woosik KIM ,  HoSuk SHIN ,  Soonho AHN ,  Hong Kyu PARK ,  Joon Hyun CHANG

IPC分类号： H01M4/485 ,  B01J19/18

CPC分类号： C01G53/006 ,  B01J19/1843 ,  B01J2219/00094 ,  B01J2219/182 ,  C01P2004/03 ,  C01P2004/52 ,  H01B1/08 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M10/052

摘要： Provided are an apparatus for preparing a cathode active material precursor for lithium secondary batteries including a cylindrical outer chamber, an inner cylinder that has the same central axis as the outer chamber and is mounted to rotatably move along the central axis, an electric motor to transfer power to rotate the inner cylinder, a reactant inlet disposed on the outer chamber, to add reactants to a space between the outer chamber and the inner cylinder, and an outlet disposed in the outer chamber, to obtain reaction products after reaction in the space between the outer chamber and the inner cylinder, and a method for preparing a cathode active material precursor for lithium secondary batteries using the apparatus.

摘要翻译： 本发明提供一种锂二次电池用正极活性物质前体的制造装置，其包括：圆筒状外室，具有与外部室相同的中心轴并安装成沿着中心轴可旋转地移动的内筒， 用于旋转内筒的功率，设置在外室上的反应物入口，以将反应物添加到外室和内筒之间的空间以及设置在外室中的出口，以在反应之后在第二 外室和内筒，以及使用该装置制备锂二次电池用正极活性物质前体的方法。

公开(公告)号：US06710465B2

公开(公告)日：2004-03-23

申请号：US10345161

申请日：2003-01-16

申请人： Seungheon Song ,  Woosik Kim ,  Hokyu Kang

发明人： Seungheon Song ,  Woosik Kim ,  Hokyu Kang

IPC分类号： H01L2711

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  Y10S257/904

摘要： A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

摘要翻译： 具有4F 2单位单元面积的可扩展双晶体管存储器（STTM）单元阵列，其中F是最小特征尺寸。 数据线和位线沿着Y轴方向交替并彼此相邻，并且字线沿着X轴方向布置。 每个STTM单元由在半导体衬底的表面处的浮置栅极MOS感测晶体管组成，在感测晶体管顶部具有垂直双侧壁栅极多隧道结屏障编程MOS晶体管。 数据线连接编程晶体管的所有源极区域，并且位线沿列方向连接感测晶体管的所有源极/漏极区域。 字线将编程晶体管的所有双侧壁栅极区域沿行方向连接。 本发明还涉及列寻址电路以及该电路的驱动方法。

公开(公告)号：US20160155741A1

公开(公告)日：2016-06-02

申请号：US14955107

申请日：2015-12-01

申请人： Je-Min YOO ,  Sangyoon KIM ,  Woosik KIM ,  Jongmil YOUN ,  Hwasung RHEE ,  Heedon JEONG

发明人： Je-Min YOO ,  Sangyoon KIM ,  Woosik KIM ,  Jongmil YOUN ,  Hwasung RHEE ,  Heedon JEONG

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L27/02

CPC分类号： H01L27/0924 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0928

摘要： A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.

摘要翻译： 半导体器件包括具有NMOS区域和PMOS区域的衬底，衬底上的器件隔离层，以限定有源散热片，以及衬底上具有与激活鳍片相交的长度方向的栅极图案，其中器件隔离层包括扩散 在各对活动翅片之间的制动区域，扩散制动区域在栅极图案的宽度方向上彼此相邻设置，并且其中，NMOS区域中的扩散制动区域的宽度不同于扩散区域的宽度 制动区域。

公开(公告)号：US06475857B1

公开(公告)日：2002-11-05

申请号：US09884912

申请日：2001-06-21

申请人： Woosik Kim ,  Seungheon Song ,  Hokyu Kang

发明人： Woosik Kim ,  Seungheon Song ,  Hokyu Kang

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： A method of fabricating a multiple tunnel junction Scalable Two-Transistor Memory (STTM) cell array with a unit cell area as low as 4F2, F representing the minimum feature dimension, which usually is the width and also the spacing of the data lines or the write (or word or control gate) lines, wherein process sequence and conditions are designed to offer wide flexibility in material choices and layer thickness at different regions of the STTM cell with surface planarity maintained at several stages of the manufacturing sequence. The processing of memory cell devices is made compatible with peripheral CMOS devices so that the devices in both areas can be made simultaneously, thereby decreasing the total number of processing steps. Insulator filled trenches around the device regions, source/drain and the gate regions of the peripheral devices are formed simultaneously with the corresponding regions of the memory cell devices.

摘要翻译： 一种制造具有低至4F2的单元单元面积的多隧道结可伸缩双晶体管存储器（STTM）单元阵列的方法，F表示最小特征尺寸，其通常是数据线的宽度和间距 写（或字或控制门）线，其中工艺顺序和条件被设计为在STTM单元的不同区域处提供在材料选择和层厚度方面的广泛的灵活性，并且在制造顺序的几个阶段保持表面平面度。 存储单元设备的处理与外围CMOS器件兼容，使得两个区域中的器件可以同时进行，从而减少处理步骤的总数。 绝缘体在器件区域周围填充沟槽，外围器件的源极/漏极和栅极区域与存储器单元器件的相应区域同时形成。

公开(公告)号：US20100296982A1

公开(公告)日：2010-11-25

申请号：US12812832

申请日：2008-06-10

申请人： Jongpal Hong ,  Hyeryeon Kang ,  Dayoung Kim ,  Changhoon Lee ,  Woosik Kim

发明人： Jongpal Hong ,  Hyeryeon Kang ,  Dayoung Kim ,  Changhoon Lee ,  Woosik Kim

IPC分类号： B01J19/18

CPC分类号： B01D9/0013 ,  B01D9/0036

摘要： Disclosed is a crystallizer comprising: a reaction bath having an inlet for feeding a reactant, an outlet for discharging a reaction product, and an inner reaction space in which a crystallization reaction is proceeded; and an agitation bar placed in the inner reaction space of the reaction bath, one cross-section of which is smaller than the other cross-section of the bar in a direction of flowing the reactant.

摘要翻译： 公开了一种结晶器，包括：反应槽，其具有用于进料反应物的入口，用于排出反应产物的出口和进行结晶反应的内部反应空间; 以及设置在反应槽的内部反应空间中的搅拌棒，一个横截面小于棒的另一个横截面沿着反应物流动的方向。

公开(公告)号：US20070123023A1

公开(公告)日：2007-05-31

申请号：US11289787

申请日：2005-11-30

申请人： Woosik Kim ,  Chanro Park

发明人： Woosik Kim ,  Chanro Park

IPC分类号： H01L21/4763

CPC分类号： H01L43/12

摘要： A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on the magnetoresistive junction element; a second non-conductive layer above the first non-conductive layer in regions over the hard mask and a second of the metallic lines; a third non-conductive layer disposed above the hard mask; and a fourth non-conductive layer disposed on the third non-conductive layer. The method further includes partially opening first and second trenches to uncover the second non-conductive layer above the hard mask and second metallic line, respectively; fully opening the first and second trenches to uncover the hard mask and second metallic line, respectively; and filling the first and second trenches with conductive material.

摘要翻译： 在磁阻存储单元中形成双互连的方法包括：提供中间产品，包括：包括金属线的金属化层; 通过第一非导电层导电地连接到第一金属线的磁阻结点; 设置在磁阻接合元件上的金属硬掩模; 在所述硬掩模上的区域中的所述第一非导电层上方的第二非导电层和所述金属线中的第二非导电层; 设置在硬掩模上方的第三非导电层; 以及设置在所述第三非导电层上的第四非导电层。 该方法还包括部分地打开第一和第二沟槽以分别露出硬掩模和第二金属线上方的第二非导电层; 分别完全打开第一和第二沟槽以揭开硬掩模和第二金属线; 以及用导电材料填充第一和第二沟槽。

公开(公告)号：US20070091674A1

公开(公告)日：2007-04-26

申请号：US11536323

申请日：2006-09-28

申请人： Human Park ,  Philippe Blanchard ,  Woosik Kim ,  Gill Lee

发明人： Human Park ,  Philippe Blanchard ,  Woosik Kim ,  Gill Lee

IPC分类号： G11C11/14

CPC分类号： G11C11/16 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06

摘要： A transistor cell and method of making a transistor cell is disclosed. In one embodiment a transistor cell, includes first metal line spacers and the first gate spacers that vertically at least partially overlap, wherein second metal line spacers and second gate spacers vertically at least partially overlap. A contact region is defined above a second source/drain region and/or a third source/drain region by a respective adjacent first metal line spacer and second metal line spacer and by a respective adjacent first gate spacer and second gate spacer. A contact via vertically extends from the contact region at least to the layer of the first metal line.

摘要翻译： 公开了一种制造晶体管单元的晶体管单元和方法。 在一个实施例中，晶体管单元包括第一金属线间隔物和垂直至少部分重叠的第一栅极间隔物，其中第二金属线隔离物和第二栅极间隔物垂直至少部分重叠。 接触区域由相应的相邻的第一金属线间隔物和第二金属线间隔物以及相应的相邻的第一栅极间隔物和第二栅极间隔物限定在第二源极/漏极区域和/或第三源极/漏极区域的上方。 接触孔从接触区域至少垂直地延伸到第一金属线的层。

公开(公告)号：US06528896B2

公开(公告)日：2003-03-04

申请号：US09884911

申请日：2001-06-21

申请人： Seungheon Song ,  Woosik Kim ,  Hokyu Kang

发明人： Seungheon Song ,  Woosik Kim ,  Hokyu Kang

IPC分类号： H01L2711

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  Y10S257/904

摘要： A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

摘要翻译： 具有4F2单位区域的可扩展双晶体管存储器（STTM）单元阵列，其中F是最小特征尺寸。 数据线和位线沿着Y轴方向交替并彼此相邻，并且字线沿着X轴方向布置。 每个STTM单元由在半导体衬底的表面处的浮置栅极MOS感测晶体管组成，在感测晶体管顶部具有垂直双侧壁栅极多隧道结屏障编程MOS晶体管。 数据线连接编程晶体管的所有源极区域，并且位线沿列方向连接感测晶体管的所有源极/漏极区域。 字线将编程晶体管的所有双侧壁栅极区域沿行方向连接。 本发明还涉及列寻址电路以及该电路的驱动方法。

公开(公告)号：US07381574B2

公开(公告)日：2008-06-03

申请号：US11289787

申请日：2005-11-30

申请人： Woosik Kim ,  Chanro Park

发明人： Woosik Kim ,  Chanro Park

IPC分类号： H01L21/00

CPC分类号： H01L43/12

摘要： A method of forming dual interconnects in a magnetoresistive memory cell includes: providing an intermediate product including: a metallization layer including metallic lines; a magnetoresistive junction element conductively connected to a first of the metallic lines by a via through a first non-conductive layer; a metallic hard mask disposed on the magnetoresistive junction element; a second non-conductive layer above the first non-conductive layer in regions over the hard mask and a second of the metallic lines; a third non-conductive layer disposed above the hard mask; and a fourth non-conductive layer disposed on the third non-conductive layer. The method further includes partially opening first and second trenches to uncover the second non-conductive layer above the hard mask and second metallic line, respectively; fully opening the first and second trenches to uncover the hard mask and second metallic line, respectively; and filling the first and second trenches with conductive material.

摘要翻译： 在磁阻存储单元中形成双互连的方法包括：提供中间产品，包括：包括金属线的金属化层; 通过第一非导电层导电地连接到第一金属线的磁阻结点; 设置在磁阻接合元件上的金属硬掩模; 在所述硬掩模上的区域中的所述第一非导电层上方的第二非导电层和所述金属线中的第二非导电层; 设置在硬掩模上方的第三非导电层; 以及设置在所述第三非导电层上的第四非导电层。 该方法还包括部分地打开第一和第二沟槽以分别露出硬掩模和第二金属线上方的第二非导电层; 分别完全打开第一和第二沟槽以揭开硬掩模和第二金属线; 以及用导电材料填充第一和第二沟槽。

公开(公告)号：US06806096B1

公开(公告)日：2004-10-19

申请号：US10464226

申请日：2003-06-18

申请人： Woosik Kim ,  Gill Yong Lee

发明人： Woosik Kim ,  Gill Yong Lee

IPC分类号： H01L2100

CPC分类号： H01L43/12 ,  H01L27/222

摘要： A method of fabricating a magnetic memory device and a magnetic memory device structure. A buffer insulating layer is deposited over the top surface of the conductive hard mask of a magnetic memory cell. The buffer insulating layer is left remaining over the conductive hard mask top surface while the various material layers of the device are patterned and etched. The buffer insulating layer prevents the conductive hard mask top surface from being damaged during plasma-containing processes.

摘要翻译： 一种制造磁存储器件和磁存储器件结构的方法。 缓冲绝缘层沉积在磁存储单元的导电硬掩模的顶表面上。 缓冲绝缘层保留在导电硬掩模顶表面上，同时对器件的各种材料层进行图案化和蚀刻。 缓冲绝缘层防止导电硬掩模顶表面在等离子体处理过程中受损。