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    Memory having cap structure for magnetoresistive junction and method for structuring the same
    1.
    发明授权
    Memory having cap structure for magnetoresistive junction and method for structuring the same 失效
    具有用于磁阻结的帽结构的存储器及其结构化方法

    公开(公告)号：US07602032B2

    公开(公告)日：2009-10-13

    申请号：US11117854

    申请日：2005-04-29

    申请人： Ulrich Klostermann ,  Chanro Park ,  Wolfgang Raberg

    发明人： Ulrich Klostermann ,  Chanro Park ,  Wolfgang Raberg

    IPC分类号： H01L29/82

    CPC分类号： G11C11/15 ,  H01L43/08 ,  H01L43/12

    摘要： A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed over an upper magnetic layer of a magnetoresistive junction (MTJ/MCJ) layered structure and a hardmask layer formed over said etch stop layer, wherein said etch stop layer is selected from a material such that an etch chemistry used for removing said hardmask layer has selectivity against etching said etch stop layer material. In a method of opening the hardmask layer, an etch process to remove exposed portions of the hardmask layer is implemented, where the etch process terminates on the etch stop layer.

    摘要翻译： 公开了一种存储器和制造存储器的方法。 在一个实施例中，存储器包括用于磁阻随机存取存储器件的盖结构，其包括形成在磁阻结（MTJ / MCJ）分层结构的上磁层上的蚀刻停止层和形成在所述蚀刻停止层上的硬掩模层， 其中所述蚀刻停止层选自材料，使得用于去除所述硬掩模层的蚀刻化学性质对蚀刻所述蚀刻停止层材料具有选择性。 在打开硬掩模层的方法中，实现去除硬掩模层的暴露部分的蚀刻工艺，其中蚀刻工艺在蚀刻停止层上终止。

    Integrated circuits and processes for forming integrated circuits having an embedded electrical interconnect within a substrate
    7.
    发明授权
    Integrated circuits and processes for forming integrated circuits having an embedded electrical interconnect within a substrate 有权
    用于形成在衬底内具有嵌入式电互连的集成电路的集成电路和工艺

    公开(公告)号：US08871635B2

    公开(公告)日：2014-10-28

    申请号：US13466895

    申请日：2012-05-08

    申请人： Chanro Park ,  Errol T. Ryan

    发明人： Chanro Park ,  Errol T. Ryan

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76883 ,  H01L21/76832 ,  H01L21/76834

    摘要： Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.

    摘要翻译： 提供了用于形成集成电路的集成电路和工艺。 用于形成集成电路的示例性方法包括提供包括氧化物层和设置在氧化物层上的保护层的衬底。 通过保护层蚀刻凹陷，并且至少部分地蚀刻到氧化物层中。 阻挡材料沉积在凹部中以在氧化物层和凹部中的保护层之上形成阻挡层。 导电材料沉积在凹槽中的势垒层上以形成嵌入的电互连。 嵌入的电互连和阻挡层分别凹陷到衬底内的互连凹槽深度和阻挡凹槽深度。 在使阻挡层凹陷之后，保护层的至少一部分保留在氧化物层上方，并且在凹陷阻挡层之后被去除。

    Methods of forming copper-based conductive structures on semiconductor devices
    8.
    发明授权
    Methods of forming copper-based conductive structures on semiconductor devices 有权
    在半导体器件上形成铜基导电结构的方法

    公开(公告)号：US08791014B2

    公开(公告)日：2014-07-29

    申请号：US13422439

    申请日：2012-03-16

    申请人： Xunyuan Zhang ,  Hoon Kim ,  Chanro Park

    发明人： Xunyuan Zhang ,  Hoon Kim ,  Chanro Park

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76879 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76816

    摘要： Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.

    摘要翻译： 本文公开了在诸如晶体管的半导体器件上形成铜基导电结构的各种方法。 在一个示例中，该方法包括通过图案化的金属硬掩模层执行第一蚀刻工艺以限定绝缘材料层中的开口，通过绝缘材料层中的开口执行第二蚀刻工艺，该开口暴露一部分 下面的含铜结构，进行湿蚀刻处理以去除图案化的金属硬掩模层，通过绝缘材料层中的开口进行选择性金属沉积工艺，以选择性地在含铜结构上形成金属区域，之后 形成金属区域，在金属区域上方的开口中形成含铜结构体。