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    Memory having cap structure for magnetoresistive junction and method for structuring the same
    1.
    发明授权
    Memory having cap structure for magnetoresistive junction and method for structuring the same 失效
    具有用于磁阻结的帽结构的存储器及其结构化方法

    公开(公告)号：US07602032B2

    公开(公告)日：2009-10-13

    申请号：US11117854

    申请日：2005-04-29

    申请人： Ulrich Klostermann ,  Chanro Park ,  Wolfgang Raberg

    发明人： Ulrich Klostermann ,  Chanro Park ,  Wolfgang Raberg

    IPC分类号： H01L29/82

    CPC分类号： G11C11/15 ,  H01L43/08 ,  H01L43/12

    摘要： A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed over an upper magnetic layer of a magnetoresistive junction (MTJ/MCJ) layered structure and a hardmask layer formed over said etch stop layer, wherein said etch stop layer is selected from a material such that an etch chemistry used for removing said hardmask layer has selectivity against etching said etch stop layer material. In a method of opening the hardmask layer, an etch process to remove exposed portions of the hardmask layer is implemented, where the etch process terminates on the etch stop layer.

    摘要翻译： 公开了一种存储器和制造存储器的方法。 在一个实施例中，存储器包括用于磁阻随机存取存储器件的盖结构，其包括形成在磁阻结（MTJ / MCJ）分层结构的上磁层上的蚀刻停止层和形成在所述蚀刻停止层上的硬掩模层， 其中所述蚀刻停止层选自材料，使得用于去除所述硬掩模层的蚀刻化学性质对蚀刻所述蚀刻停止层材料具有选择性。 在打开硬掩模层的方法中，实现去除硬掩模层的暴露部分的蚀刻工艺，其中蚀刻工艺在蚀刻停止层上终止。

    Memory cell using spin induced switching effects
    6.
    发明授权
    Memory cell using spin induced switching effects 失效
    存储单元使用自旋感应开关效应

    公开(公告)号：US07715225B2

    公开(公告)日：2010-05-11

    申请号：US12036518

    申请日：2008-02-25

    申请人： Wolfgang Raberg ,  Ulrich Klostermann

    发明人： Wolfgang Raberg ,  Ulrich Klostermann

    IPC分类号： G11C11/00

    CPC分类号： H01L27/222 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

    摘要： According to an embodiment, an integrated circuit includes a magneto-resistive memory cell. The magneto-resistive memory cell includes: a first ferromagnetic layer; a second ferromagnetic layer; and a nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer. The integrated circuit further includes a programming circuit configured to route a programming current through the magneto-resistive memory cell, wherein the programming current programs the magnetizations of the first ferromagnetic layer and of the second ferromagnetic layer by spin induced switching effects.

    摘要翻译： 根据实施例，集成电路包括磁阻存储单元。 磁阻存储单元包括：第一铁磁层; 第二铁磁层; 并且非磁性层设置在第一铁磁层和第二铁磁层之间。 集成电路还包括编程电路，其被配置为将编程电流路由到磁阻存储器单元，其中编程电流通过自旋感应开关效应对第一铁磁层和第二铁磁层的磁化进行编程。

    MRAM structure using sacrificial layer for anti-ferromagnet and method of manufacture
    7.
    发明申请
    MRAM structure using sacrificial layer for anti-ferromagnet and method of manufacture 有权
    用于抗铁磁体的牺牲层的MRAM结构及其制造方法

    公开(公告)号：US20070278602A1

    公开(公告)日：2007-12-06

    申请号：US11448170

    申请日：2006-06-06

    申请人： Wolfgang Raberg ,  Ulrich Klostermann

    发明人： Wolfgang Raberg ,  Ulrich Klostermann

    IPC分类号： H01L43/00

    CPC分类号： H01L43/08 ,  H01L43/12

    摘要： A magnetic random access memory structure comprising an anti-ferromagnetic layer structure, a crystalline ferromagnetic structure physically coupled to the anti-ferromagnetic layer structure and a ferromagnetic free layer structure physically coupled to the crystalline ferromagnetic structure.

    摘要翻译： 磁性随机存取存储器结构包括反铁磁层结构，物理耦合到反铁磁层结构的结晶铁磁结构和物理耦合到结晶铁磁结构的铁磁自由层结构。

    Small, scalable resistive element and method of manufacturing
    8.
    发明申请
    Small, scalable resistive element and method of manufacturing 审中-公开
    小型，可扩展的电阻元件和制造方法

    公开(公告)号：US20050014342A1

    公开(公告)日：2005-01-20

    申请号：US10622422

    申请日：2003-07-18

    申请人： Daniel Worledge ,  Ulrich Klostermann ,  Wolfgang Raberg ,  Stephen Brown

    发明人： Daniel Worledge ,  Ulrich Klostermann ,  Wolfgang Raberg ,  Stephen Brown

    IPC分类号： H01C7/00 ,  H01L21/02 ,  H01L27/08 ,  H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L28/24 ,  H01C7/006 ,  H01L27/0802

    摘要： An improved scalable, resistive element for use in a semiconductor device that can be produced with a small feature size and precise resistance is provided by the present invention. The resistive element includes a base layer positioned on top of a metal line. A seed layer of is deposited on top of the base layer. A thin barrier layer of Al is deposited on top of the seed layer and oxidized. A non-magnetic metal layer is then deposited on top of the barrier layer. The base layer and the non-magnetic metal layer form electrodes on either side of the barrier layer. The barrier layer is thin enough that a tunneling current can travel between the electrodes. The resulting resistive element may be constructed with a high resistance and a very small feature size.

    摘要翻译： 通过本发明提供了一种用于半导体器件的改进的可扩展的电阻元件，其可以以小的特征尺寸和精确的电阻产生。 电阻元件包括位于金属线顶部的基层。 种子层沉积在基层的顶部。 Al的薄势垒层沉积在种子层的顶部并被氧化。 然后将非磁性金属层沉积在阻挡层的顶部上。 基极层和非磁性金属层在势垒层的两侧形成电极。 阻挡层足够薄，使得隧道电流可以在电极之间行进。 所得到的电阻元件可以被构造成具有高电阻和非常小的特征尺寸。

    Integrated Circuit, Memory Cell Arrangement, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing a Memory Cell
    9.
    发明申请
    Integrated Circuit, Memory Cell Arrangement, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing a Memory Cell 失效
    集成电路，存储单元布置，存储单元，存储器模块，操作集成电路的方法和制造存储单元的方法

    公开(公告)号：US20090213642A1

    公开(公告)日：2009-08-27

    申请号：US12036518

    申请日：2008-02-25

    申请人： Wolfgang Raberg ,  Ulrich Klostermann

    发明人： Wolfgang Raberg ,  Ulrich Klostermann

    IPC分类号： G11C11/16 ,  G11C11/22 ,  H01L21/8239

    CPC分类号： H01L27/222 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08

    摘要： According to an embodiment, an integrated circuit includes a magneto-resistive memory cell. The magneto-resistive memory cell includes: a first ferromagnetic layer; a second ferromagnetic layer; and a nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer. The integrated circuit further includes a programming circuit configured to route a programming current through the magneto-resistive memory cell, wherein the programming current programs the magnetizations of the first ferromagnetic layer and of the second ferromagnetic layer by spin induced switching effects.

    摘要翻译： 根据实施例，集成电路包括磁阻存储单元。 磁阻存储单元包括：第一铁磁层; 第二铁磁层; 并且非磁性层设置在第一铁磁层和第二铁磁层之间。 集成电路还包括编程电路，其被配置为将编程电流路由到磁阻存储器单元，其中编程电流通过自旋感应开关效应对第一铁磁层和第二铁磁层的磁化进行编程。