公开(公告)号：US6127229A

公开(公告)日：2000-10-03

申请号：US301222

申请日：1999-04-29

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： There is presented an improved method of fabricating an EEPROM device with a split gate. In the method, a silicon substrate is provided having spaced and parallel recessed oxide regions that isolate component regions where the oxide regions project above the top surface of the substrate. A thin gate oxide is formed on the substrate, and a first conformal layer is deposited over the gate oxide and projecting oxide regions. The substrate is then chemical-mechanically polished to remove the projections of polysilicon over the oxide regions. A silicon nitride layer is deposited on the resultant planar surface of the polysilicon, and elongated openings formed that will define the position of the floating gates that are perpendicular to the oxide regions. The exposed polysilicon in the openings in the silicon nitride are oxidized down to at least the level of the underlying silicon oxide regions, and the silicon nitride layer removed. The polysilicon layer is then removed using the silicon oxide layer as an etch barrier, and the edge surfaces of the resulting polysilicon floating gates oxidized. A second polysilicon layer is deposited on the substrate and elongated word lines formed that are parallel and partially overlapping the floating gates. Source lines are formed in the substrate, and gate lines are formed that overlie the floating gates.

摘要翻译： 提出了一种用分裂栅极制造EEPROM器件的改进方法。 在该方法中，提供硅衬底，其具有间隔开且平行的凹陷氧化物区域，其隔离氧化物区域突出在衬底的顶表面上方的组分区域。 在衬底上形成薄栅氧化物，并且在栅极氧化物和突出的氧化物区域上沉积第一共形层。 然后将衬底进行化学机械抛光以去除多晶硅在氧化物区域上的突起。 在所形成的多晶硅的平坦表面上沉积氮化硅层，形成将形成垂直于氧化物区域的浮栅的位置的细长开口。 氮化硅中的开口中的暴露的多晶硅被氧化到至少下面的氧化硅区域的水平，并且去除了氮化硅层。 然后使用氧化硅层作为蚀刻阻挡层去除多晶硅层，并且所得多晶硅浮栅的边缘表面被氧化。 第二多晶硅层沉积在衬底上，并且形成平行且部分地与浮动栅极重叠的细长字线。 在衬底中形成源极线，并且形成覆盖浮栅的栅极线。

公开(公告)号：US6117733A

公开(公告)日：2000-09-12

申请号：US193670

申请日：1998-11-17

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L21/336 ,  H01L29/72 ,  H01L31/00

CPC分类号： H01L29/42324 ,  H01L27/11519 ,  H01L27/11521

摘要： A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch is formed after wet oxidizing the sidewalls of the underlying first polysilicon layer, thus at the same time forming a poly tip which is exposed upwardly but covered by polyoxide on the side. In another embodiment, the notch is formed prior to the oxidation of the exposed regions of the first polysilicon layer, such as the sidewalls, so that during the subsequent oxidation, not only the sidewalls but also the exposed portions of the polysilicon in the notch region are also oxidized. Because the oxidation of the polysilicon advances in a non-uniform manner with very little at the polysilicon/nitride interface and to a larger rate elsewhere, a thin and robust polysilicon tip is formed which is at the same time covered by oval-shaped poly-oxide on all sides. A method of forming a self-aligned source (SAS) line is also disclosed in conjunction with the forming of the polytip. Hence the combination of an enhanced poly tip with a self-aligned source provides a faster split-gate flash memory device.

摘要翻译： 公开了一种用于形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多头）的新方法。 通过在覆盖第一多晶硅层的氮化物层中以两种不同的方式形成凹口来进一步增强多晶硅尖端。 在一个实施例中，凹陷是在湿氧化下面的第一多晶硅层的侧壁之后形成的，因此同时形成向上暴露但被侧面被多氧化物覆盖的多边尖端。 在另一个实施例中，在第一多晶硅层（例如侧壁）的暴露区域的氧化之前形成凹口，使得在随后的氧化期间，不仅侧壁而且在凹口区域中的多晶硅的暴露部分 也被氧化。 由于多晶硅的氧化以非均匀的方式在多晶硅/氮化物界面处以非常小的速度前进，并且在其它地方以更大的速率前进，形成了薄而坚固的多晶硅尖端，同时被椭圆形多晶硅/ 氧化物在所有方面。 结合形成聚丝片也公开了形成自对准源（SAS）线的方法。 因此，增强型多头尖端与自对准源的组合提供了更快的分离栅极闪存器件。

公开(公告)号：US6090668A

公开(公告)日：2000-07-18

申请号：US248725

申请日：1999-02-11

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a sharp poly tip which substantially improves the erase speed of the cell. The poly tip is formed without the need for conventional oxidation of the polysilicon floating gate. Instead, the polysilicon layer is etched using a high pressure recipe thereby forming a recess with a sloped profile into the polysilicon layer. The recess is filled with a top-oxide, which in turn serves as a hard mask in etching those portions of the polysilicon year not protected by the top-oxide layer. The edge of the polysilicon layer formed by the sloping walls of the recess forms the sharp poly tip of this invention. The sharp tip does not experience the damage caused by conventional poly oxidation processes and, therefore, provides enhanced erase speed for the split-gate flash memory cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种用于形成具有尖锐多边尖端的分裂栅极闪存单元的方法，其基本上改善了单元的擦除速度。 形成多边形，而不需要多晶硅浮动栅极的常规氧化。 相反，使用高压配方蚀刻多晶硅层，从而形成具有倾斜轮廓的凹陷到多晶硅层中。 凹部填充有顶部氧化物，其又用作蚀刻多晶硅年份未被顶部氧化物层保护的那些部分的硬掩模。 由凹陷的倾斜壁形成的多晶硅层的边缘形成本发明的尖锐的多边形尖端。 锋利的尖端不会经历由常规聚氧化过程引起的损坏，因此为分离式闪存单元提供增强的擦除速度。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US06355527B1

公开(公告)日：2002-03-12

申请号：US09314588

申请日：1999-05-19

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的耦合比和改进的程序速度的分离栅极闪存单元的方法。 还提供了分离栅极单元，其中第一多晶硅层形成布置在形成在形成控制栅极的第二多晶硅层上的中间栅极氧化物上的浮置栅极。 然而，第二多晶硅层也形成在源极区上方并且覆盖浮置栅极的另一个另外暴露的部分，使得该附加多线现在共享源极和浮置栅极之间的电压，从而减少穿通和结击穿 电压。 此外，沿浮置栅极的另一个多壁的存在增加了源极和浮置栅极之间的耦合比，这进而提高了分离栅极闪存单元的编程速度。

公开(公告)号：US06249454B1

公开(公告)日：2001-06-19

申请号：US09396519

申请日：1999-09-15

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.

公开(公告)号：US06207503B1

公开(公告)日：2001-03-27

申请号：US09133970

申请日：1998-08-14

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 以掩模盖的图案形成由隧道氧化物层和浮栅电极层形成的栅电极堆叠。 在覆盖堆叠和源极区域和漏极区域的衬底上方形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 将栅极电极堆叠的中心的源极线槽图案化为衬底。 通过源线槽形成源区。 形成漏极区域与分离栅电极和栅极电极堆叠自对准。

公开(公告)号：US06174772B1

公开(公告)日：2001-01-16

申请号：US09347548

申请日：1999-07-06

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

摘要翻译： 公开了一种形成具有形成在衬垫氧化物上的氮化物间隔物并且之前形成多晶氧化物层的分裂栅极快闪存储器单元的方法。 以这种方式，避免了在形成多晶硅氧化物之前在氮化物间隔物的蚀刻期间多晶氧化物通常会发生的任何损伤。 因此，通过反转形成间隔物和多晶氧化物的顺序，包括首先形成衬垫氧化物，也可以避免由于对下面的间隔物的不可预测的损伤而导致的多晶氧化物厚度的变化 。 结果，对于在同一晶片上以及相同或不同生产线上的不同晶片上制造的单元，都能够防止栅极间闪存单元的擦除速度的变化。

公开(公告)号：US6165845A

公开(公告)日：2000-12-26

申请号：US298931

申请日：1999-04-26

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided to form a sharp poly tip to improve the speed of a split-gate flash memory. The sharp poly tip is provided in place of the conventional gate bird's beak (GBB) because the latter requires the forming of thick poly-oxide which is more and more difficult in the miniaturized circuits of the ultra scale integrated technology. Furthermore, it is well known that GBB encroaches under the gate edge in a split-gate flash and degrades the programmability of submicron memory cells. The sharp poly tip of the invention is provided by forming a tapered floating gate through a high pressure etch such that the tip of the upper edge of the floating gate under the poly oxide is sharper and more robust, and, therefore, less susceptible to damage during the manufacture of the cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种形成尖锐的多晶硅尖端以提高分流栅闪存的速度的方法。 提供尖锐的多头尖端来代替常规的门鸟嘴（GBB），因为后者需要形成在超级集成技术的小型化电路中越来越困难的厚的多晶氧化物。 此外，众所周知，GBB在分割门闪存中的栅极边缘下侵入并降低亚微米存储器单元的可编程性。 通过高压蚀刻形成锥形浮栅，使得多晶氧化物下方的浮栅的上边缘的尖端更清晰，更坚固，因此不易受损害，从而提供本发明的尖锐的多尖端 在电池的制造期间。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US6093608A

公开(公告)日：2000-07-25

申请号：US298142

申请日：1999-04-23

申请人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

发明人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate. The P-channel flash memory cell has a higher impact ionization rage for creating hot electrons so that the distance between the source and drain junctions and the length of the floating gate can be kept small thereby permitting the dimensions of the flash memory cell to be shrunk.

公开(公告)号：US5976927A

公开(公告)日：1999-11-02

申请号：US58120

申请日：1998-04-10

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-cheng Sung

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-cheng Sung

IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L21/8247 ,  H01L21/76

CPC分类号： H01L27/10844 ,  H01L21/76202 ,  H01L27/11517

摘要： A method for forming a field oxide isolation regions of a memory array is described. The field isolation regions comprise a rectangular array of oxide islands. The oxide islands are formed by a two mask process wherein the first mask is a LOCOS hardmask which defines an array of parallel field oxide stripes. The field oxide stripes are thermally grown by a LOCOS oxidation process. A second mask, which has an array of parallel stripes perpendicular to the field oxide stripes is then patterned over the wafer. The stripes of the second mask expose a plurality of narrow sections of the field oxide stripes which are then etched by a directional plasma etch having a high selectivity of silicon oxide over silicon. The anisotropic etch segments each of the longer oxide stripes into a string of islands space apart by a narrow gap through which a robust common source line passes unencumbered by birdsbeak oxide. The edges of the field oxide at the gap have vertical walls and square corners which afford improved spacing of components in the vicinity of the gap. The method eliminates the need for a mask bias to accommodate corner rounding and birdsbeak oxide encroachment which occurs if the islands are defined by a single mask process.

摘要翻译： 描述了形成存储器阵列的场氧化物隔离区域的方法。 场隔离区域包括氧化物岛的矩形阵列。 氧化物岛通过两个掩模工艺形成，其中第一掩模是定义平行场氧化物条纹阵列的LOCOS硬掩模。 场氧化物条纹通过LOCOS氧化工艺热生长。 然后将具有垂直于场氧化物条纹的平行条纹阵列的第二掩模图案化在晶片上。 第二掩模的条纹暴露出场氧化物条纹的多个窄部分，然后通过硅上的氧化硅选择性高的定向等离子体蚀刻来蚀刻。 各向异性蚀刻将较长的氧化物条中的每一个划分成岛状空间，间隔狭窄的间隙，坚固的公共源极线穿过该间隙不受鸟笼氧化物阻碍。 间隙处的场氧化物的边缘具有垂直壁和方角，其提供间隙附近的部件的间隔改善。 该方法消除了掩模偏压的需要，以适应拐角倒圆和鸟瞰氧化物侵蚀，如果岛由单个掩模过程定义，则会发生。