Recordable disk recording controller with batch register controller
    21.
    发明授权
    Recordable disk recording controller with batch register controller 有权
    具有批次寄存器控制器的可记录磁盘记录控制器

    公开(公告)号:US06795893B2

    公开(公告)日:2004-09-21

    申请号:US09748447

    申请日:2000-12-22

    IPC分类号: G06F1200

    摘要: In a recordable disk recording controller circuit, a data buffer manager receives a command and sends the command to a micro-controller. The micro-controller generates a set of register batches from each command and sends the register data and index of the register batch to a batch register controller. The batch register controller receives the register data and index of the register batch from the micro-controller and stores the received register data and index of the register batch in a batch buffer. The batch register controller retrieves the register batches from the batch buffer and writes the master registers of an encoder controller based on the register index and register data of the register batches after the master registers of the encoder controller are updated into the slave registers of the encoder controller. The encoder controller generates control signals to a recording circuit depending on updated slave registers. Such control signals cause the recording circuit to record a signal representative of signal data on a recordable disk located in a recordable disk driver.

    摘要翻译: 在可记录盘记录控制器电路中,数据缓冲器管理器接收命令并将命令发送到微控制器。 微控制器从每个命令生成一组寄存器批,并将寄存器批次的寄存器数据和索引发送到批量寄存器控制器。 批处理寄存器控制器从微控制器接收寄存器数据的寄存器数据和索引,并将接收到的寄存器数据和寄存器批次的索引存储在批量缓冲器中。 批量寄存器控制器从批量缓冲器中检索寄存器批次,并在编码器控制器的主寄存器更新到编码器的从寄存器之后,基于寄存器索引和寄存器批次的寄存器数据写入编码器控制器的主寄存器 控制器。 编码器控制器根据更新的从机寄存器向记录电路生成控制信号。 这种控制信号使得记录电路将表示信号数据的信号记录在位于可记录磁盘驱动器中的可记录盘上。

    INTEGRATED APPARATUS FOR MULTI-STANDARD OPTICAL STORAGE MEDIA
    22.
    发明申请
    INTEGRATED APPARATUS FOR MULTI-STANDARD OPTICAL STORAGE MEDIA 有权
    用于多标准光存储介质的集成设备

    公开(公告)号:US20090217134A1

    公开(公告)日:2009-08-27

    申请号:US12433229

    申请日:2009-04-30

    IPC分类号: H03M13/05 G06F11/10

    摘要: An integrated apparatus for multi-standard optical media includes a compact disc/digital versatile disc (CD/DVD) processor, a high-definition DVD (HDDVD) processor and a Blu-ray disc (BD) processor; a memory unit connected to the CD/DVD processor, the HDDVD processor and the BD processor to provide a storage resource; and a shared error correction code (ECC) engine for encoding or decoding the CD/DVD data stream, the HDDVD data stream and the BD data stream. Therein, the ECC engine further has a syndrome/parity generator to encode the data stream or to obtain the syndrome information from the data stream; and an erasure generator to obtain the possible error position information from the data stream. Thereby, the complexity and cost of the integrated apparatus can be reduced.

    摘要翻译: 用于多标准光学介质的集成设备包括光盘/数字通用盘(CD / DVD)处理器,高清DVD(HDDVD)处理器和蓝光盘(BD)处理器) 连接到CD / DVD处理器的存储器单元,HDDVD处理器和BD处理器以提供存储资源; 以及用于对CD / DVD数据流进行编码或解码的共享纠错码(ECC)引擎,HDDVD数据流和BD数据流。 其中,ECC引擎还具有对数据流进行编码或从数据流获取校正子信息的校正子/奇偶校验发生器; 以及擦除发生器,以从数据流中获取可能的错误位置信息。 由此,能够降低集成装置的复杂性和成本。

    Link writing method for a recordable or rewritable compact disk and drive for using the method
    24.
    发明授权
    Link writing method for a recordable or rewritable compact disk and drive for using the method 有权
    用于可记录或可重写光盘的链接写入方法和使用该方法的驱动器

    公开(公告)号:US07023780B2

    公开(公告)日:2006-04-04

    申请号:US09800896

    申请日:2001-03-08

    IPC分类号: G11B7/0045

    摘要: A link writing method for a recordable or rewritable compact disk includes recording a writing interruption address and enabling a succeeding writing process after the writing interruption. Enabling a succeeding writing process includes searching the linking area and enabling a start writing signal and activating a laser power. The method can link a succeeding writing area with a previously written interrupted area with sufficient accuracy to allow the data frame to be successfully processed by error correction within the host drive. The linking area may be positioned by counting the values of the interrupted block, the interrupted data frame, and the interrupted bit count or by detecting a blank area. Other techniques for positioning the linking area include detecting an unwritten area having a length greater than a maximum or writing a characteristic pattern after an interruption.

    摘要翻译: 用于可记录或可重写的光盘的链接写入方法包括在写入中断之后记录写入中断地址并使得能够进行后续的写入处理。 启用成功的写入过程包括搜索链接区域并启用开始写入信号并激活激光功率。 该方法可以将后续写入区域与先前写入的中断区域以足够的精度进行链接,从而通过主机驱动器内的纠错来成功地处理数据帧。 可以通过对中断的块的值,中断的数据帧和中断的比特数进行计数或通过检测空白区域来定位链接区域。 用于定位链接区域的其他技术包括检测长度大于最大值的未写入区域或在中断之后写入特征图案。

    Link writing method for a recordable or rewritable compact disk and drive for using the method
    25.
    发明申请
    Link writing method for a recordable or rewritable compact disk and drive for using the method 有权
    用于可记录或可重写光盘的链接写入方法和使用该方法的驱动器

    公开(公告)号:US20050281160A1

    公开(公告)日:2005-12-22

    申请号:US11214192

    申请日:2005-08-29

    摘要: A link writing method for a recordable or rewritable compact disk includes recording a writing interruption address and enabling a succeeding writing process after the writing interruption. Enabling a succeeding writing process includes searching the linking area and enabling a start writing signal and activating a laser power. The method can link a succeeding writing area with a previously written interrupted area with sufficient accuracy to allow the data frame to be successfully processed by error correction within the host drive. The linking area may be positioned by counting the values of the interrupted block, the interrupted data frame, and the interrupted bit count or by detecting a blank area. Other techniques for positioning the linking area include detecting an unwritten area having a length greater than a maximum or writing a characteristic pattern after an interruption.

    摘要翻译: 用于可记录或可重写的光盘的链接写入方法包括在写入中断之后记录写入中断地址并使得能够进行后续的写入处理。 启用成功的写入过程包括搜索链接区域并启用开始写入信号并激活激光功率。 该方法可以将后续写入区域与先前写入的中断区域以足够的精度进行链接,从而通过主机驱动器内的纠错来成功地处理数据帧。 可以通过对中断的块的值,中断的数据帧和中断的比特数进行计数或通过检测空白区域来定位链接区域。 用于定位链接区域的其他技术包括检测长度大于最大值的未写入区域或在中断之后写入特征图案。

    Digital sum variation computation method and system

    公开(公告)号:US20050094755A1

    公开(公告)日:2005-05-05

    申请号:US11002514

    申请日:2004-12-01

    IPC分类号: G11B20/14 H04B14/04

    摘要: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

    Adaptive-selection method for memory access priority control in MPEG
processor
    27.
    发明授权
    Adaptive-selection method for memory access priority control in MPEG processor 失效
    MPEG处理器中存储器访问优先级控制的自适应选择方法

    公开(公告)号:US5982360A

    公开(公告)日:1999-11-09

    申请号:US941064

    申请日:1997-09-30

    摘要: An adaptive-selection method for memory access priority control in MPEG processor. The processor has functional modules that include an input interface, a CPU, an audio decoder, a video decoder, an audio processor, a video processor and a memory controller. Each of the modules gains control over the data bus via arbitration by the memory controller for accessing the memory. The access priority of the CPU to the data bus is maintained at a relatively lower level except when the CPU needs to perform parsing on the MPEG compressed data and implementing the initial decoding of the audio compressed data. The use of data bus bandwidth is therefore balanced among all the system resources thereby increasing the overall system performance.

    摘要翻译: 一种用于MPEG处理器中存储器访问优先级控制的自适应选择方法。 处理器具有包括输入接口,CPU,音频解码器,视频解码器,音频处理器,视频处理器和存储器控制器的功能模块。 每个模块通过存储器控制器的仲裁来获得对数据总线的控制以访问存储器。 除CPU需要对MPEG压缩数据进行解析并实现音频压缩数据的初始解码之外,CPU对数据总线的访问优先级保持在相对较低的水平。 因此,在所有系统资源之间平衡使用数据总线带宽,从而提高整个系统的性能。