公开(公告)号：US09413573B2

公开(公告)日：2016-08-09

申请号：US12317160

申请日：2008-12-19

申请人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04L27/00 ,  H03G3/30 ,  H04B3/23 ,  H04B3/32 ,  H04L25/03

CPC分类号： H04L27/0002 ,  H03G3/3068 ,  H04B3/23 ,  H04B3/32 ,  H04L25/03057 ,  H04L2025/0349

摘要： An analog and digital auto-gain control method includes the steps of: providing a gain-mapping table; determining an analog gain level according to a power of a far-end transmitted signal; obtaining a gain-mapping value from the gain-mapping table according to the analog gain level; obtaining a digital gain value according to the gain-mapping value; and adjusting a gain of a digital signal according to the digital gain value. A receiver that performs the auto-gain control method is also disclosed.

摘要翻译： 模拟和数字自动增益控制方法包括以下步骤：提供增益映射表; 根据远端发射信号的功率确定模拟增益电平; 根据模拟增益水平从增益映射表获取增益映射值; 根据增益映射值获得数字增益值; 以及根据数字增益值调整数字信号的增益。 还公开了执行自动增益控制方法的接收机。

公开(公告)号：US08204152B2

公开(公告)日：2012-06-19

申请号：US12107761

申请日：2008-04-22

申请人： Fong-Ching Huang ,  Chih-Yung Shih

发明人： Fong-Ching Huang ,  Chih-Yung Shih

IPC分类号： H04L27/00

CPC分类号： H04L7/0029 ,  H04L7/0012 ,  H04L7/0079 ,  H04L25/03044

摘要： A digitally synchronized receiving device and an associated signal processing method are provided. The digitally synchronized receiving device can receive data transmitted by a transmitter. The transmitter and the receiving device belong to a first clock domain and a second clock domain respectively. The receiving device performs synchronization in a digital manner, so as to deal with the problem of the analog solution in prior arts and the synchronization for interference cancellation.

摘要翻译： 提供了一种数字同步的接收设备和相关的信号处理方法。 数字同步的接收设备可以接收由发射机发送的数据。 发射机和接收设备分别属于第一时钟域和第二时钟域。 接收装置以数字方式执行同步，以便处理现有技术中的模拟解决方案的问题和用于干扰消除的同步。

公开(公告)号：US07933196B2

公开(公告)日：2011-04-26

申请号：US12250528

申请日：2008-10-13

申请人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04J3/10

CPC分类号： H04B3/32 ,  H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03566

摘要： An apparatus for channel interference cancellation includes a first interference-cancellation module and a first cancellation-signal generating circuit. The first interference-cancellation module comprises a first processing circuit including a grouping circuit and a first transforming circuit. The grouping circuit divides received data into a plurality of groups of first sub-data. The first transforming circuit sequentially transforms the groups of first sub-data from a first domain to a second domain to generate a plurality of groups of first transformed sub-data. The first cancellation-signal generating circuit comprises a delay unit, a first processing unit and a second processing unit. The delay unit sequentially delays the groups of first transformed sub-data to generate a plurality of groups of delayed sub-data. The first and the second processing unit output a first and a second processed signal according to the groups of first transformed sub-data and the groups of delayed sub-data respectively.

摘要翻译： 用于信道干扰消除的装置包括第一干扰消除模块和第一抵消信号发生电路。 第一干扰消除模块包括包括分组电路和第一变换电路的第一处理电路。 分组电路将接收到的数据分成多组第一子数据。 第一变换电路将第一子数据组从第一域顺序地变换到第二域，以产生多组第一变换子数据。 第一抵消信号发生电路包括延迟单元，第一处理单元和第二处理单元。 延迟单元顺序地延迟第一变换子数据组以生成多组延迟子数据。 第一和第二处理单元分别根据第一变换子数据组和延迟子数据组输出第一和第二处理信号。

公开(公告)号：US20090180409A1

公开(公告)日：2009-07-16

申请号：US12350929

申请日：2009-01-08

申请人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04B3/20

CPC分类号： H04B3/32 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885 ,  H04L2025/03477 ,  H04L2025/03484 ,  H04L2025/03605

摘要： A network apparatus for eliminating interference between transport ports includes a plurality of transport ports and at least one alien NEXT canceller. The alien NEXT canceller is coupled to a designated transport port of the plurality of transport ports for eliminating NEXT interference from other transport ports of the plurality of transport ports. The alien NEXT canceller operates in a time domain or a frequency domain. In one exemplary embodiment, the network apparatus is a switch.

摘要翻译： 用于消除传输端口之间的干扰的网络设备包括多个传输端口和至少一个外来NEXT消除器。 外来NEXT消除器耦合到多个传输端口的指定传输端口，用于消除多个传输端口中其他传输端口的NEXT干扰。 外来NEXT消除器在时域或频域中运行。 在一个示例性实施例中，网络设备是开关。

公开(公告)号：US20090109834A1

公开(公告)日：2009-04-30

申请号：US12260101

申请日：2008-10-29

申请人： Liang-wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04J3/10 ,  H04L12/56

CPC分类号： H04B3/32 ,  H04B3/23 ,  H04L49/10

摘要： A network apparatus with a plurality of transport ports and a shared coefficient update processor is proposed. Each of the plurality of transport ports includes a PHY module. The coefficient update processor is coupled to each PHY module and is shared by the plurality of transport ports. The coefficient update processor decides coefficients of each PHY module. The coefficient update processor is dedicated to one of the plurality of transport ports for use in a period of time.

摘要翻译： 提出了具有多个传输端口和共享系数更新处理器的网络设备。 多个传输端口中的每一个包括PHY模块。 系数更新处理器耦合到每个PHY模块并由多个传输端口共享。 系数更新处理器决定每个PHY模块的系数。 系数更新处理器专用于多个传输端口中的一个，用于一段时间。

公开(公告)号：US20090097394A1

公开(公告)日：2009-04-16

申请号：US12250528

申请日：2008-10-13

申请人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04J3/10

CPC分类号： H04B3/32 ,  H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03566

摘要： An apparatus for channel interference cancellation includes a first interference-cancellation module and a first cancellation-signal generating circuit. The first interference-cancellation module comprises a first processing circuit including a grouping circuit and a first transforming circuit. The grouping circuit divides received data into a plurality of groups of first sub-data. The first transforming circuit sequentially transforms the groups of first sub-data from a first domain to a second domain to generate a plurality of groups of first transformed sub-data. The first cancellation-signal generating circuit comprises a delay unit, a first processing unit and a second processing unit. The delay unit sequentially delays the groups of first transformed sub-data to generate a plurality of groups of delayed sub-data. The first and the second processing unit output a first and a second processed signal according to the groups of first transformed sub-data and the groups of delayed sub-data respectively.

摘要翻译： 用于信道干扰消除的装置包括第一干扰消除模块和第一抵消信号发生电路。 第一干扰消除模块包括包括分组电路和第一变换电路的第一处理电路。 分组电路将接收到的数据分成多组第一子数据。 第一变换电路将第一子数据组从第一域顺序地变换到第二域，以产生多组第一变换子数据。 第一抵消信号发生电路包括延迟单元，第一处理单元和第二处理单元。 延迟单元顺序地延迟第一变换子数据组以生成多组延迟子数据。 第一和第二处理单元分别根据第一变换子数据组和延迟子数据组输出第一和第二处理信号。

公开(公告)号：US20080189234A1

公开(公告)日：2008-08-07

申请号：US12022449

申请日：2008-01-30

申请人： Chih-Yung Shih

发明人： Chih-Yung Shih

IPC分类号： G06N5/02

CPC分类号： G06F7/22 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/658 ,  H03M13/6583

摘要： The present invention relates to a search circuit in a decoding unit of low-density parity-check codes, which used for searching a minimum value and a next minimum value from r input values, where r is an integer greater than 3. The search circuit includes a first search circuit and a second search circuit. The search method includes performing operations on each pair of input values Vi, Vj of the r input values, respectively. The second search circuit, which is coupled to the first search circuit, performs operations on every two sets of compared values Wm, Lm, and Wn, Ln of the s compared values, where s is a positive integer smaller than r, the smaller value Wm is smaller than the greater value Lm, and the smaller value Wn is smaller than the greater value Ln. The second search circuit performs operations according to the smaller value Wo and the greater value Lo to produce the minimum value and the next minimum value. Thereby, the search of the minimum value, the next minimum value, and the address of the minimum value can be performed at the same time without the need of waiting completion of search for the minimum value then the next minimum vale can be searched.

摘要翻译： 本发明涉及低密度奇偶校验码的解码单元中的搜索电路，其用于从r个输入值搜索最小值和下一个最小值，其中r是大于3的整数。搜索电路 包括第一搜索电路和第二搜索电路。 搜索方法包括分别对r个输入值的每对输入值Vi，Vj执行操作。 耦合到第一搜索电路的第二搜索电路对s比较值的每两组比较值Wm，Lm和Wn，Ln进行操作，其中s是小于r的正整数，较小值 Wm小于较大值Lm，并且较小值Wn小于较大值Ln。 第二搜索电路根据较小的值Wo和较大的值Lo执行操作以产生最小值和下一个最小值。 因此，可以同时执行最小值，下一个最小值和最小值的地址的搜索，而不需要等待完成搜索最小值，然后可以搜索下一个最小值。

公开(公告)号：US09252994B2

公开(公告)日：2016-02-02

申请号：US12260099

申请日：2008-10-29

申请人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04J3/06 ,  H04L25/14 ,  H04L7/00 ,  H04L25/03

CPC分类号： H04L25/14 ,  H04J3/0685 ,  H04L7/0029 ,  H04L7/0079 ,  H04L2025/03369 ,  H04L2025/03477

摘要： A network apparatus, for processing a network signal and outputting an output signal, includes an asynchronous signal processing module, a sampling rate converter and a synchronous signal processing module. The asynchronous signal processing module operates in an asynchronous domain, and is utilized for receiving and processing the network signal to generate a first processed signal. The sampling rate converter is coupled to the asynchronous signal processing module, and is utilized for performing sampling rate conversion on the first processed signal to generate the output signal. A first operating frequency of the asynchronous signal processing module is different from a second operating frequency of the synchronous signal processing module.

摘要翻译： 用于处理网络信号并输出​​输出信号的网络装置包括异步信号处理模块，采样率转换器和同步信号处理模块。 异步信号处理模块在异步域中操作，并用于接收和处理网络信号以产生第一处理信号。 采样率转换器耦合到异步信号处理模块，并用于对第一处理信号进行采样率转换以产生输出信号。 异步信号处理模块的第一工作频率与同步信号处理模块的第二工作频率不同。

公开(公告)号：US09112265B2

公开(公告)日：2015-08-18

申请号：US13609090

申请日：2012-09-10

申请人： Tzuh-Suan Wang ,  Yu-Fu Kuo ,  Yuan-Chin Hsu ,  Chih-Yung Shih

发明人： Tzuh-Suan Wang ,  Yu-Fu Kuo ,  Yuan-Chin Hsu ,  Chih-Yung Shih

IPC分类号： H01P11/00 ,  H01Q1/24 ,  H01Q1/38

CPC分类号： H01Q1/243 ,  H01Q1/38 ,  Y10T29/49016

摘要： A method for manufacturing an antenna structure is disclosed. Employing steps of mixing with a catalyst and embedding a metal insert can simplify steps for manufacturing the antenna structure. Further, a non-conductive frame produced by the process disclosed herein can exhibit waterproof effect. The catalyst mentioned above is mixed with a plastic and then injected into a mold to form the non-conductive frame. The metal insert mentioned above is disposed in the mold before the step of injecting the plastic. Alternatively, the metal insert is embedded in the non-conductive frame after the step of injecting the plastic.

摘要翻译： 公开了一种用于制造天线结构的方法。 采用与催化剂混合并嵌入金属插入物的步骤可以简化制造天线结构的步骤。 此外，通过本文公开的方法制造的非导电框架可以表现出防水效果。 将上述催化剂与塑料混合，然后注入模具以形成非导电性框架。 上述金属插入件在注射塑料的步骤之前设置在模具中。 或者，在注塑塑料的步骤之后，将金属插入件嵌入非导电框架中。

公开(公告)号：US08532167B2

公开(公告)日：2013-09-10

申请号：US12356081

申请日：2009-01-20

申请人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

发明人： Liang-Wei Huang ,  Chih-Yung Shih ,  Shieh-Hsing Kuo

IPC分类号： H04L27/01

CPC分类号： H04L25/03012

摘要： The present invention provides a signal processing device. The signal processing device includes a first feed forward equalizing unit, a first data slicing unit, a second feed forward equalizing unit, and a second data slicing unit. The first feed forward equalizing unit is utilized for performing a compensation operation according to a digital input signal so as to generate a first equalized signal. The first data slicing unit is coupled to the first feed forward equalizing unit, and utilized for generating a first output signal according to the first equalized signal. The second feed forward equalizing unit is coupled to the first data slicing unit, and utilized for generating a second equalized signal according to the first equalized signal. The second data slicing unit is coupled to the second feed forward equalizing unit, and utilized for generating a second output signal according to the second equalized signal.

摘要翻译： 本发明提供一种信号处理装置。 信号处理装置包括第一前馈均衡单元，第一数据限幅单元，第二前馈均衡单元和第二数据限幅单元。 第一前馈均衡单元用于根据数字输入信号执行补偿操作，以产生第一均衡信号。 第一数据切片单元耦合到第一前馈均衡单元，用于根据第一均衡信号产生第一输出信号。 第二前馈均衡单元耦合到第一数据限幅单元，用于根据第一均衡信号产生第二均衡信号。 第二数据限幅单元耦合到第二前馈均衡单元，用于根据第二均衡信号产生第二输出信号。